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Date: Thu, 1 Feb 2024 13:11:39 +0000
From: Conor Dooley <conor.dooley@microchip.com>
To: Frank Wunderlich <frank-w@public-files.de>
CC: Conor Dooley <conor@kernel.org>, AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>, Frank Wunderlich
	<linux@fw-web.de>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd
	<sboyd@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Philipp Zabel
	<p.zabel@pengutronix.de>, Rob Herring <robh+dt@kernel.org>, Krzysztof
 Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley
	<conor+dt@kernel.org>, Sam Shih <sam.shih@mediatek.com>, Daniel Golle
	<daniel@makrotopia.org>, <linux-clk@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-mediatek@lists.infradead.org>
Subject: Re: Aw: Re: [PATCH v3 1/2] dt-bindings: reset: mediatek: add MT7988
 reset IDs
Message-ID: <20240201-goes-passable-0ba841d36bc3@wendy>
References: <20240117184111.62371-1-linux@fw-web.de>
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On Thu, Feb 01, 2024 at 12:40:17PM +0100, Frank Wunderlich wrote:
> Am 19. Januar 2024 18:04:36 MEZ schrieb Conor Dooley <conor@kernel.org>:
> >On Fri, Jan 19, 2024 at 10:28:30AM +0100, AngeloGioacchino Del Regno wro=
te:
> >>
> >> The resets are organized on a per-reset-controller basis, so, the ETHW=
ARP
> >> reset controller's first reset is RST_SWITCH, the second one is RST_so=
mething_else,
> >> etc. while the first reset of the INFRA reset controller is PEXTP_MAC_=
SWRST.
> >>=20
> >> That's why ETHWARP has a reset index 0 and INFRA also starts at 0.
> >> I think that the numbering is good as it is, and having one driver sta=
rt at index 5
> >> while the other starts at index 12 would only overcomplicate registeri=
ng the resets
> >> in each driver, or waste bytes by making unnecessarily large arrays, f=
or (imo) no
> >> good reason.
> >>=20
> >> This is one header, but it should "in theory" be more than one... so w=
e would have
> >> one for each hardware block - but that'd make the reset directory over=
-crowded, as
> >> other MediaTek SoCs have got even more resets in even more hardware bl=
ocks than the
> >> MT7988. That'd be something like ~4 reset headers per SoC (and will in=
crease with
> >> newer ones)...
> >> ...and this is why we have one binding header for resets.
> >
> >That's okay. The commit message leaves me, who clearly isn't a mediatek
> >guy, with no information as to why these are not one contiguous set.
> >IMO being for different reset controllers entirely is fine.
> >
> >> On the topic of leaving space to allow grouping RST0/RST1: -> No. <-
> >> The indices have to start from zero and have to be sequential, with no=
 holes.
> >
> >Agreed.
>=20
> Hi,
>=20
> Just a friendly reminder.
>=20
> As far as i understood, Patches are fine so far and do not need any rewor=
k,right?

I suspect I was asking for a commit message that explains why these
numbers don't continue in sequence. With that,
Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

>=20
> But i have not seen them picked up yet in linux-next.
> regards Frank

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