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Shutemov" To: Paolo Bonzini Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Zixi Chen , Adam Dunlap , Xiaoyao Li , Kai Huang , Dave Hansen , Thomas Gleixner , Ingo Molnar , x86@kernel.org, stable@vger.kernel.org Subject: Re: [PATCH v2 2/2] x86/cpu/intel: Detect TME keyid bits before setting MTRR mask registers Message-ID: References: <20240131230902.1867092-1-pbonzini@redhat.com> <20240131230902.1867092-3-pbonzini@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240131230902.1867092-3-pbonzini@redhat.com> On Thu, Feb 01, 2024 at 12:09:02AM +0100, Paolo Bonzini wrote: > MKTME repurposes the high bit of physical address to key id for encryption > key and, even though MAXPHYADDR in CPUID[0x80000008] remains the same, > the valid bits in the MTRR mask register are based on the reduced number > of physical address bits. > > detect_tme() in arch/x86/kernel/cpu/intel.c detects TME and subtracts > it from the total usable physical bits, but it is called too late. > Move the call to early_init_intel() so that it is called in setup_arch(), > before MTRRs are setup. > > This fixes boot on TDX-enabled systems, which until now only worked with > "disable_mtrr_cleanup". Without the patch, the values written to the > MTRRs mask registers were 52-bit wide (e.g. 0x000fffff_80000800) and > the writes failed; with the patch, the values are 46-bit wide, which > matches the reduced MAXPHYADDR that is shown in /proc/cpuinfo. > > Reported-by: Zixi Chen > Cc: Adam Dunlap > Cc: Kirill A. Shutemov > Cc: Xiaoyao Li > Cc: Kai Huang > Cc: Dave Hansen > Cc: Thomas Gleixner > Cc: Ingo Molnar > Cc: x86@kernel.org > Cc: stable@vger.kernel.org > Signed-off-by: Paolo Bonzini Reviewed-by: Kirill A. Shutemov -- Kiryl Shutsemau / Kirill A. Shutemov