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Date: Thu, 1 Feb 2024 15:22:40 +0100
From: Andi Shyti <andi.shyti@kernel.org>
To: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Cc: andersson@kernel.org, konrad.dybcio@linaro.org, 
	linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, 
	vkoul@kernel.org, quic_bjorande@quicinc.com, manivannan.sadhasivam@linaro.org, 
	bryan.odonoghue@linaro.org, quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com, 
	Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Subject: Re: [V3] i2c: i2c-qcom-geni: Correct I2C TRE sequence
Message-ID: <dt2uwtff5yacr7ci7xbezbe7bpwxsvspimceat7cozhzgazszx@6cjp5r7abfqd>
References: <20240201101323.13676-1-quic_vdadhani@quicinc.com>
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In-Reply-To: <20240201101323.13676-1-quic_vdadhani@quicinc.com>

Hi Viken,

On Thu, Feb 01, 2024 at 03:43:23PM +0530, Viken Dadhaniya wrote:
> For i2c read operation in GSI mode, we are getting timeout
> due to malformed TRE basically incorrect TRE sequence
> in gpi(drivers/dma/qcom/gpi.c) driver.
> 
> TRE stands for Transfer Ring Element - which is basically an element with
> size of 4 words. It contains all information like slave address,
> clk divider, dma address value data size etc).
> 
> Mainly we have 3 TREs(Config, GO and DMA tre).
> - CONFIG TRE : consists of internal register configuration which is
>                required before start of the transfer.
> - DMA TRE :    contains DDR/Memory address, called as DMA descriptor.
> - GO TRE :     contains Transfer directions, slave ID, Delay flags, Length
>                of the transfer.
> 
> Driver calls GPI driver API to config each TRE depending on the protocol.
> If we see GPI driver, for RX operation we are configuring DMA tre and
> for TX operation we are configuring GO tre.
> 
> For read operation tre sequence will be as below which is not aligned
> to hardware programming guide.
> 
> - CONFIG tre
> - DMA tre
> - GO tre
> 
> As per Qualcomm's internal Hardware Programming Guide, we should configure
> TREs in below sequence for any RX only transfer.
> 
> - CONFIG tre
> - GO tre
> - DMA tre
> 
> In summary, for RX only transfers, we are reordering DMA and GO TREs.
> Tested covering i2c read/write transfer on QCM6490 RB3 board.
> 
> Fixes: d8703554f4de ("i2c: qcom-geni: Add support for GPI DMA")
> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>

as Dmitry has written, please, next time don't forget the tags:

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # qrb5165-rb5

You can also add mine:

Reviewed-by: Andi Shyti <andi.shyti@kernel.org> 

Please make sure to Cc Dmitry who is raising his concerns and
check on his comments.

Andi

PS just as a reminder, if Dmitry's concerns remain related only
to the commit log, I gave you the option to agree with him in the
e-mail thread without necessarily sending a v4. I can then update
the commit log before pushing.