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Fri, 2 Feb 2024 04:31:11 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 1 Feb 2024 20:31:11 -0800 Date: Thu, 1 Feb 2024 20:31:10 -0800 From: Elliot Berman To: Charlie Jenkins CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green , =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , , Subject: Re: [PATCH v2 2/2] riscv: Disable misaligned access probe when CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS Message-ID: Mail-Followup-To: Charlie Jenkins , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green , =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org References: <20240201-disable_misaligned_probe_config-v2-0-77c368bed7b2@rivosinc.com> <20240201-disable_misaligned_probe_config-v2-2-77c368bed7b2@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240201-disable_misaligned_probe_config-v2-2-77c368bed7b2@rivosinc.com> X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: v2zNNbLEzggt0GdOtik2j8HK7sQEwjcC X-Proofpoint-ORIG-GUID: v2zNNbLEzggt0GdOtik2j8HK7sQEwjcC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-01_10,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 mlxlogscore=631 suspectscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 clxscore=1011 adultscore=0 spamscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402020030 Hi Charlie, On Thu, Feb 01, 2024 at 03:30:46PM -0800, Charlie Jenkins wrote: > When CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is selected, the cpus can be > set to have fast misaligned access without needing to probe. > > Signed-off-by: Charlie Jenkins > --- > arch/riscv/Kconfig | 1 + > arch/riscv/include/asm/cpufeature.h | 7 + > arch/riscv/include/asm/misaligned_access_speed.h | 29 +++ > arch/riscv/kernel/Makefile | 3 + > arch/riscv/kernel/cpufeature.c | 255 ---------------------- > arch/riscv/kernel/misaligned_access_speed.c | 265 +++++++++++++++++++++++ > arch/riscv/kernel/sys_hwprobe.c | 4 + > 7 files changed, 309 insertions(+), 255 deletions(-) > > diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile > index f71910718053..8be7f17da9ab 100644 > --- a/arch/riscv/kernel/Makefile > +++ b/arch/riscv/kernel/Makefile > @@ -62,6 +62,9 @@ obj-y += tests/ > obj-$(CONFIG_MMU) += vdso.o vdso/ > > obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o > +ifneq ($(RISCV_EFFICIENT_UNALIGNED_ACCESS), y) Should this be CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS ? > +obj-y += misaligned_access_speed.o > +endif > obj-$(CONFIG_FPU) += fpu.o > obj-$(CONFIG_RISCV_ISA_V) += vector.o > obj-$(CONFIG_RISCV_ISA_V) += kernel_mode_vector.o