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Date: Fri, 2 Feb 2024 14:56:31 +0100
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Subject: Re: [PATCH v2] dt-bindings: media: Add sram-size Property for Wave5
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To: Nishanth Menon <nm@ti.com>
Cc: Brandon Brnich <b-brnich@ti.com>, Nas Chung <nas.chung@chipsnmedia.com>,
 Jackson Lee <jackson.lee@chipsnmedia.com>,
 Mauro Carvalho Chehab <mchehab@kernel.org>, Rob Herring
 <robh+dt@kernel.org>, Krzysztof Kozlowski
 <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>,
 linux-media@vger.kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org, Vignesh Raghavendra <vigneshr@ti.com>,
 Darren Etheridge <detheridge@ti.com>
References: <20240201184238.2542695-1-b-brnich@ti.com>
 <1209b7cf-5be2-4107-aa6b-d67a32ea3737@linaro.org>
 <20240202125257.p4astjuxpzr5ltjs@dragster>
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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In-Reply-To: <20240202125257.p4astjuxpzr5ltjs@dragster>
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On 02/02/2024 13:52, Nishanth Menon wrote:
> On 11:47-20240202, Krzysztof Kozlowski wrote:
>> On 01/02/2024 19:42, Brandon Brnich wrote:
>>> Wave521c has capability to use SRAM carveout to store reference data with
>>> purpose of reducing memory bandwidth. To properly use this pool, the driver
>>> expects to have an sram and sram-size node. Without sram-size node, driver
>>> will default value to zero, making sram node irrelevant.
>>
>> I am sorry, but what driver expects should not be rationale for new
>> property. This justification suggests clearly it is not a property for DT.
>>
> 
> Yup, the argumentation in the commit message is from the wrong
> perspective. bindings are OS agnostic hardware description, and what
> driver does with the description is driver's problem.
> 
> I will at least paraphrase my understanding:
> In this case, however, the hardware block will limp along with
> the usage of DDR (as is the current description), due to the
> latencies involved for DDR accesses. However, the hardware block
> has capability to use a substantially lower latency SRAM to provide
> proper performance and hence for example, deal with higher resolution
> data streams. This SRAM is instantiated at SoC level rather than
> embedded within the hardware block itself.

That sounds like OS policy. Why would different boards with the same
component have this set differently? Based on amount of available
memory? This, I believe, is runtime configuration because it might
depend on user-space you run. Based on purpose (e.g. optimize for
decoding or general usage)? Again, run-time because same hardware board
can be used for different purposes.

Best regards,
Krzysztof