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From: Frank Li <Frank.Li@nxp.com>
Date: Fri, 02 Feb 2024 10:11:25 -0500
Subject: [PATCH v3 3/6] PCI: dwc: Add outbound MSG TLPs support
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To: Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>, 
 Gustavo Pimentel <gustavo.pimentel@synopsys.com>, 
 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, 
 Lorenzo Pieralisi <lpieralisi@kernel.org>, 
 =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>, 
 Rob Herring <robh@kernel.org>, 
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, 
 Conor Dooley <conor+dt@kernel.org>, imx@lists.linux.dev
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, 
 devicetree@vger.kernel.org, Frank Li <Frank.Li@nxp.com>, 
 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>, 
 Serge Semin <fancer.lancer@gmail.com>
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 =?utf-8?B?bkZqOUhuOWRVNCtmVHdtTlpmbGpiaUViSkg3am9JSmUxTnBwZWJlTndWVEhP?=
 =?utf-8?B?TlNPZENFc045RGpzcjR5NjlLY1lPa1J2aDc1MnBhdTlRWm8yUi9tOVFzMUQy?=
 =?utf-8?B?OWtmczdDREI2cGtFWTBYaVdmakNSMENndGRBbU80WURLSXg0Mkd6cTNmYlJ6?=
 =?utf-8?B?ZUplLzBBLzg1ZFRUeW5JK1FBWGJITVBUMjREM3R2d1BlaTRWWlU5WGo3VERD?=
 =?utf-8?B?L3l3NE9Wbk9WSUtzWXdxaDFrRFNnR0dwWWVHaFdaMmkrbmF6QjlsckUwL0xB?=
 =?utf-8?B?LzI1ZjE2Z3hPeEFHeFRSWWg4YWdxbzF3ZGI0K2ZMRHhWcTN6NmMwc0tER3Nn?=
 =?utf-8?B?V0VDMi9PVXJzU1JFQjIxcXlxdU9iL1FRL3dydjVDejRyNlpEZkYvbDhZM0N0?=
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 =?utf-8?B?eXdNVWZNeWVWVTVCeTc1K1l3MU9ObVdwQXlKNGkzOWdaT1EyZjRrL1ZXR1Zy?=
 =?utf-8?B?TFFhYnUreUY5V3NuTFliYWdnU0hacGFBQjA1bXBSWW43dm85WmsxNUNac1Rl?=
 =?utf-8?B?UFUwbC9NWXR5UW5uYkJkMjFvNEJtUUtJMWExNlIxVWIwWHNTeFdiOGZWY0JK?=
 =?utf-8?B?bzUxN05XUy9UUWNqU0cra1VtZ3RBeXNyaHhGTWM3SGQrenY4K1AyemJsSHdB?=
 =?utf-8?B?QzlZK3VEREtOTkQ3MHVoMXlEOXNQN2MxSWprWmhGVm1uZmxOOHpsN3BQVzEy?=
 =?utf-8?B?cFVuZFlCTXRnZnJkbmNsUU11Q1crRUJrbWs3VGtYT3dudk1Lekg0cktFdElt?=
 =?utf-8?B?NmNNUjNZL3BONWRUUXhia0svR25aYzl6VXVDTWZvUzdXL2tPUGVuT2V5SjFl?=
 =?utf-8?B?RldmcUpiTmJMa0tQQWZEY3BoMm9TQnRQVTA1ZkF2Q2ROY1FZNmFtM3NHNHlT?=
 =?utf-8?B?U2Z5VVVGZjEzZWlHV2hlaSs5c1FadElKYzdCeWo0NUNkTDYvT1ZIcm5haGlB?=
 =?utf-8?Q?KAONvc65CVhZRneG5I3q6s8qD?=
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From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for triggering
INTx IRQs by iATU in the PCIe endpoint mode in near the future.
PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
MsgD. So, this implementation supports the data-less messages only
for now.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
 drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index df2575ec5f44c..ba909fade9db1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -499,7 +499,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
 			      upper_32_bits(atu->pci_addr));
 
-	val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
+	val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
 	if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
 	    dw_pcie_ver_is_ge(pci, 460A))
 		val |= PCIE_ATU_INCREASE_REGION_SIZE;
@@ -507,7 +507,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 		val = dw_pcie_enable_ecrc(val);
 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
 
-	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
+	val = PCIE_ATU_ENABLE;
+	if (atu->type == PCIE_ATU_TYPE_MSG) {
+		/* The data-less messages only for now */
+		val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
+	}
+	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
 
 	/*
 	 * Make sure ATU enable takes effect before any subsequent config
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index d21db82e586d5..703b50bc5e0f1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -148,11 +148,13 @@
 #define PCIE_ATU_TYPE_IO		0x2
 #define PCIE_ATU_TYPE_CFG0		0x4
 #define PCIE_ATU_TYPE_CFG1		0x5
+#define PCIE_ATU_TYPE_MSG		0x10
 #define PCIE_ATU_TD			BIT(8)
 #define PCIE_ATU_FUNC_NUM(pf)           ((pf) << 20)
 #define PCIE_ATU_REGION_CTRL2		0x004
 #define PCIE_ATU_ENABLE			BIT(31)
 #define PCIE_ATU_BAR_MODE_ENABLE	BIT(30)
+#define PCIE_ATU_INHIBIT_PAYLOAD	BIT(22)
 #define PCIE_ATU_FUNC_NUM_MATCH_EN      BIT(19)
 #define PCIE_ATU_LOWER_BASE		0x008
 #define PCIE_ATU_UPPER_BASE		0x00C
@@ -303,6 +305,8 @@ struct dw_pcie_ob_atu_cfg {
 	int index;
 	int type;
 	u8 func_no;
+	u8 code;
+	u8 routing;
 	u64 cpu_addr;
 	u64 pci_addr;
 	u64 size;

-- 
2.34.1