Received-SPF: pass (google.com: domain of linux-kernel+bounces-51148-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
Precedence: bulk
MIME-Version: 1.0
References: <20240202093907.9465-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20240202093907.9465-2-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240202-explain-harsh-b5d81cb5f59a@spud>
In-Reply-To: <20240202-explain-harsh-b5d81cb5f59a@spud>
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: Sat, 3 Feb 2024 15:27:52 +0000
Message-ID: <CA+V-a8u--97k82xUdCnCRqo7cj+JAkmzAgcZqnD2neSGvtgznQ@mail.gmail.com>
Subject: Re: [PATCH 1/3] dt-bindings: interrupt-controller:
 renesas,rzg2l-irqc: Update interrupts
To: Conor Dooley <conor@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, 
	devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, 
	linux-kernel@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, 
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

Hi Conor,

Thank you for the review.

On Fri, Feb 2, 2024 at 5:07=E2=80=AFPM Conor Dooley <conor@kernel.org> wrot=
e:
>
> On Fri, Feb 02, 2024 at 09:39:05AM +0000, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > RZ/{G2L, G2LC}, RZ/G2UL, RZ/V2L and RZ/G3S SoCs have ECCRAM0/1 interrup=
ts,
> > reflect the same in the DT binding doc.
>
> Renesas' naming scheme really does not help here, but using the
> shorthands in the commit message when the diff uses the long form names
> is not the easiest thing to follow. (:
>
Sure I'll elabore the SoCs according to the binding doc so that it's more c=
lear.
> >
> > RZ/G3S SoC has ECCRAM0/1 interrupts combined into single interrupts so
> > we just use the below to represent them:
> > - ec7tie1-0
> > - ec7tie2-0
> > - ec7tiovf-0
>
> I think this information would be good in the itemised description,
> since that claims these interrupt are only for ECCRAM0.
>
Sure 'll update as below:

+      - const: ec7tie1-0   # For RZ/G3S SoC ECCRAM0/1 interrupts combined
+      - const: ec7tie2-0   # For RZ/G3S SoC ECCRAM0/1 interrupts combined
+      - const: ec7tiovf-0  # For RZ/G3S SoC ECCRAM0/1 interrupts combined

>
> > Additionally mark 'interrupt-names' property as required for all the So=
Cs
> > and update the example node in the binding doc.
>
> Why? You've not given a reason for doing this, so it just seems
> gratuitous.
>
Previous assumption was just the RZ/G2UL and RZ/G3S had the bus-err
and eccram error interrupts, but where as in actual all the above SoCs
have this interrupt so making interrupt-names as required so we can
parse them based on names.

Cheers,
Prabhakar