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Sat, 03 Feb 2024 08:54:01 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Cc: marex@denx.de, alexander.stein@ew.tq-group.com, frieder.schrempf@kontron.de, Lucas Stach , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Vinod Koul , Kishon Vijay Abraham I , Catalin Marinas , Will Deacon , Liu Ying , Ulf Hansson , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org Subject: [PATCH V8 06/12] arm64: dts: imx8mp: add HDMI irqsteer Date: Sat, 3 Feb 2024 10:52:46 -0600 Message-ID: <20240203165307.7806-7-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240203165307.7806-1-aford173@gmail.com> References: <20240203165307.7806-1-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Lucas Stach The HDMI irqsteer is a secondary interrupt controller within the HDMI subsystem that maps all HDMI peripheral IRQs into a single upstream IRQ line. Signed-off-by: Lucas Stach --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 5c54073de615..5e51a766f3d9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1399,6 +1399,19 @@ hdmi_blk_ctrl: blk-ctrl@32fc0000 { "hdcp", "hrv"; #power-domain-cells = <1>; }; + + irqsteer_hdmi: interrupt-controller@32fc2000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x32fc2000 0x44>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + fsl,channel = <1>; + fsl,num-irqs = <64>; + clocks = <&clk IMX8MP_CLK_HDMI_APB>; + clock-names = "ipg"; + power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; + }; }; aips5: bus@30c00000 { -- 2.43.0