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[209.85.208.42]) by smtp.gmail.com with ESMTPSA id vb9-20020a170907d04900b00a36814670cbsm2845979ejc.62.2024.02.03.23.41.58 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 03 Feb 2024 23:41:58 -0800 (PST) Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-55a90a0a1a1so4275668a12.0 for ; Sat, 03 Feb 2024 23:41:58 -0800 (PST) X-Received: by 2002:a05:6402:1507:b0:55f:f73d:c63b with SMTP id f7-20020a056402150700b0055ff73dc63bmr2660980edw.20.1707032517833; Sat, 03 Feb 2024 23:41:57 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240202-exception_ip-v2-0-e6894d5ce705@flygoat.com> In-Reply-To: From: Linus Torvalds Date: Sun, 4 Feb 2024 07:41:41 +0000 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 0/3] Handle delay slot for extable lookup To: Jiaxun Yang Cc: Oleg Nesterov , Thomas Bogendoerfer , Andrew Morton , Ben Hutchings , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-mm@kvack.org, Xi Ruoyao Content-Type: text/plain; charset="UTF-8" On Sat, 3 Feb 2024 at 13:56, Jiaxun Yang wrote: > > Given that exception_ip is guarded by !user_mode(regs), EPC must points > to a kernel text address. There is no way accessing kernel text will generate such > exception.. Sadly, that's not actually likely true. The thing is, the only reason for the code in get_mmap_lock_carefully() is for kernel bugs. IOW, some kernel bug with a wild pointer, and we do not want to deadlock on the mm semaphore, we want to get back to the fault handler and it should report an oops. .. and one of the "wild pointers" might in fact be the instruction pointer, in case we've branched through a NULL function pointer or similar. IOW, the exception *source* might be the instruction pointer itself. So I realy think that MIPS needs to have some kind of "safe kernel exception pointer" helper. One that is guaranteed not to fault when evaluating the exception pointer. Assuming the kernel itself is never built with MIPS16e instructions, maybe that's a safe assumption thanks to the "get_isa16_mode()" check of EPC. But all of this makes me nervous. Linus