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Date: Sun, 4 Feb 2024 16:30:05 +0800
From: Xu Yilun <yilun.xu@linux.intel.com>
To: Kris Chaplin <kris.chaplin@amd.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Charles Perry <charles.perry@savoirfairelinux.com>, mdf@kernel.org,
	"michal.simek@amd.com" <michal.simek@amd.com>, hao.wu@intel.com,
	yilun.xu@intel.com, trix@redhat.com,
	krzysztof.kozlowski+dt@linaro.org, bcody@markem-imaje.com,
	avandiver@markem-imaje.com, linux-fpga@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT
 schema
Message-ID: <Zb9LDQP3xzrv6LWr@yilunxu-OptiPlex-7050>
References: <20240129225602.3832449-1-charles.perry@savoirfairelinux.com>
 <20240129225602.3832449-2-charles.perry@savoirfairelinux.com>
 <9b0680b6-1952-41d3-82f4-88c60469dc3a@linaro.org>
 <471d9438-e2c0-4881-8ace-778c9d14669c@amd.com>
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In-Reply-To: <471d9438-e2c0-4881-8ace-778c9d14669c@amd.com>

On Wed, Jan 31, 2024 at 11:03:25AM +0000, Kris Chaplin wrote:
> Hello Krzysztof,
> 
> On 30/01/2024 16:09, Krzysztof Kozlowski wrote:
> 
> > > +
> > > +description: |
> > > +  Xilinx 7 Series FPGAs support a method of loading the bitstream over a
> > > +  parallel port named the slave SelectMAP interface in the documentation. Only
> > > +  the x8 mode is supported where data is loaded at one byte per rising edge of
> > > +  the clock, with the MSB of each byte presented to the D0 pin.
> > > +
> > > +  Datasheets:
> > > +    https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
> > 
> > I am surprised that AMD/Xilinx still did not update the document to
> > modern naming (slave->secondary).
> 
> Thank you for bringing this up.
> 
> We are moving away from using non-inclusive technical terminology and are
> removing non-inclusive language from our products and related collateral.
> You will for some time find examples of non-inclusive language, especially
> in our older products as we work to make these changes and align with
> industry standards.  For new IP we're ensuring that we switch and stick to
> inclusive terminology, as you may have seen with my recent w1 driver
> submission.
> 
> SelectMAP is a decades-old interface and as such it is unlikely that we will
> update this in all documentation dating back this time.  I shall however
> look to understand what is planned here for active documentation and new
> driver submissions.

Yes, I need review from AMD/Xilinx side. Especially the HW parts, and
some namings of variables, e.g. if xilinx-core is proper for what products
it supports, and won't be an issue in future.

Thanks,
Yilun

> 
> regards
> Kris
>