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Mon, 5 Feb 2024 03:24:23 GMT Received: from [10.253.38.98] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 4 Feb 2024 19:24:19 -0800 Message-ID: <05253a6d-7fa5-4c32-af6f-cda0f902cf77@quicinc.com> Date: Mon, 5 Feb 2024 11:24:16 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [net-next PATCH v2 2/3] net: mdio: ipq4019: add support for clock-frequency property Content-Language: en-US To: Andrew Lunn CC: Christian Marangi , Andy Gross , Bjorn Andersson , Konrad Dybcio , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Robert Marko , , , , References: <20240130003546.1546-1-ansuelsmth@gmail.com> <20240130003546.1546-3-ansuelsmth@gmail.com> <7d86388d-15f5-4e72-b99f-aee3b47a5232@quicinc.com> <4cd01d93-7b6d-4766-8337-c4dc09aeedc2@lunn.ch> From: Jie Luo In-Reply-To: <4cd01d93-7b6d-4766-8337-c4dc09aeedc2@lunn.ch> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4eiG2ulv9_zSk7S7PwD1Oa1jz-ca5GBS X-Proofpoint-GUID: 4eiG2ulv9_zSk7S7PwD1Oa1jz-ca5GBS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-04_14,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 clxscore=1011 spamscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402050025 On 2/4/2024 11:22 PM, Andrew Lunn wrote: > On Sun, Feb 04, 2024 at 05:59:10PM +0800, Jie Luo wrote: >> >> >> On 1/30/2024 8:35 AM, Christian Marangi wrote: >>> + >>> + /* If div is /256 assume nobody have set this value and >>> + * try to find one MDC rate that is close the 802.3 spec of >>> + * 2.5MHz >>> + */ >>> + for (div = 256; div >= 8; div /= 2) { >>> + /* Stop as soon as we found a divider that >>> + * reached the closest value to 2.5MHz >>> + */ >>> + if (DIV_ROUND_UP(ahb_rate, div) > 2500000) >>> + break; >> >> Hi Christian, >> Sorry for the delayed review. >> >> The MDIO hardware block supports higher frequency 6.25M and 12.5M, >> Would you remove this 2.5MHZ limitation? On the IPQ platform, we >> normally use 6.25MHZ. > > 802.3 says the clock has a maximum of 2.5MHz. So this code is correct. > > It is however O.K. to go faster, but since that breaks the standard, > you need each board to indicate it knows all the devices on the bus do > support higher speeds and its O.K. to break the standard. You indicate > this by using the DT property in its .dts file. For an MDIO bus which > is totally internal, you could however put the DT property in the SoC > .dtsi file. > > Andrew Understand it, Thanks Andrew.