Received-SPF: pass (google.com: domain of linux-kernel+bounces-52142-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
From: Alexander Stein <alexander.stein@ew.tq-group.com>
To: linux-arm-kernel@lists.infradead.org, Adam Ford <aford173@gmail.com>
Cc: marex@denx.de, frieder.schrempf@kontron.de, Lucas Stach <l.stach@pengutronix.de>, Adam Ford <aford173@gmail.com>, Andrzej Hajda <andrzej.hajda@intel.com>, Neil Armstrong <neil.armstrong@linaro.org>, Robert Foss <rfoss@kernel.org>, Laurent Pinchart <Laurent.pinchart@ideasonboard.com>, Jonas Karlman <jonas@kwiboo.se>, Jernej Skrabec <jernej.skrabec@gmail.com>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>, Maarten Lankhorst <maarten.lankhorst@linux.intel.com>, Maxime Ripard <mripard@kernel.org>, Thomas Zimmermann <tzimmermann@suse.de>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, Philipp Zabel <p.zabel@pengutronix.de>, Vinod Koul <vkoul@kernel.org>, Kishon Vijay Abraham I <kishon@kernel.org>,
  Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>, Liu Ying <victor.liu@nxp.com>, Ulf Hansson <ulf.hansson@linaro.org>, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org
Subject: Re: [PATCH V8 11/12] arm64: dts: imx8mp: add HDMI display pipeline
Date: Mon, 05 Feb 2024 08:29:50 +0100
Message-ID: <2924284.e9J7NaK4W3@steina-w>
Organization: TQ-Systems GmbH
In-Reply-To: <20240203165307.7806-12-aford173@gmail.com>
References: <20240203165307.7806-1-aford173@gmail.com> <20240203165307.7806-12-aford173@gmail.com>
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="iso-8859-1"

Hi Adam,

thanks for working on this.

Am Samstag, 3. Februar 2024, 17:52:51 CET schrieb Adam Ford:
> From: Lucas Stach <l.stach@pengutronix.de>
>=20
> This adds the DT nodes for all the peripherals that make up the
> HDMI display pipeline.
>=20
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>=20
> ---
> V2:  I took this from Lucas' original submission with the following:
>      Removed extra clock from HDMI-TX since it is now part of the
>      power domain
>      Added interrupt-parent to PVI
>      Changed the name of the HDMI tranmitter to fsl,imx8mp-hdmi-tx
>      Added ports to HDMI-tx
> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 94 +++++++++++++++++++++++
>  1 file changed, 94 insertions(+)
>=20
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> 5e51a766f3d9..e84b4f40e570 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1412,6 +1412,100 @@ irqsteer_hdmi: interrupt-controller@32fc2000 {
>  				clock-names =3D "ipg";
>  				power-domains =3D <&hdmi_blk_ctrl=20
IMX8MP_HDMIBLK_PD_IRQSTEER>;
>  			};
> +
> +			hdmi_pvi: display-bridge@32fc4000 {
> +				compatible =3D "fsl,imx8mp-hdmi-pvi";
> +				reg =3D <0x32fc4000 0x40>;
> +				interrupt-parent =3D <&irqsteer_hdmi>;
> +				interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>;

irqsteer_hdmi has #interrupt-cells =3D <1>, so IRQ flags should be removed.=
=20
dtbs_check also warns about this.

> +				power-domains =3D <&hdmi_blk_ctrl=20
IMX8MP_HDMIBLK_PD_PVI>;
> +
> +				ports {
> +					#address-cells =3D <1>;
> +					#size-cells =3D <0>;
> +
> +					port@0 {
> +						reg =3D <0>;
> +						pvi_from_lcdif3:=20
endpoint {
> +							remote-
endpoint =3D <&lcdif3_to_pvi>;
> +						};
> +					};
> +
> +					port@1 {
> +						reg =3D <1>;
> +						pvi_to_hdmi_tx:=20
endpoint {
> +							remote-
endpoint =3D <&hdmi_tx_from_pvi>;
> +						};
> +					};
> +				};
> +			};
> +
> +			lcdif3: display-controller@32fc6000 {
> +				compatible =3D "fsl,imx8mp-lcdif";
> +				reg =3D <0x32fc6000 0x238>;
> +				interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH>;

irqsteer_hdmi has #interrupt-cells =3D <1>, so IRQ flags should be removed.=
=20
dtbs_check also warns about this.

> +				interrupt-parent =3D <&irqsteer_hdmi>;
> +				clocks =3D <&hdmi_tx_phy>,
> +					 <&clk IMX8MP_CLK_HDMI_APB>,
> +					 <&clk=20
IMX8MP_CLK_HDMI_ROOT>;
> +				clock-names =3D "pix", "axi",=20
"disp_axi";
> +				power-domains =3D <&hdmi_blk_ctrl=20
IMX8MP_HDMIBLK_PD_LCDIF>;
> +
> +				port {
> +					lcdif3_to_pvi: endpoint {
> +						remote-endpoint =3D=20
<&pvi_from_lcdif3>;
> +					};
> +				};
> +			};
> +
> +			hdmi_tx: hdmi@32fd8000 {
> +				compatible =3D "fsl,imx8mp-hdmi-tx";
> +				reg =3D <0x32fd8000 0x7eff>;
> +				interrupts =3D <0 IRQ_TYPE_LEVEL_HIGH>;

irqsteer_hdmi has #interrupt-cells =3D <1>, so IRQ flags should be removed.=
=20
dtbs_check also warns about this.

> +				interrupt-parent =3D <&irqsteer_hdmi>;
> +				clocks =3D <&clk IMX8MP_CLK_HDMI_APB>,
> +					 <&clk=20
IMX8MP_CLK_HDMI_REF_266M>,
> +					 <&clk IMX8MP_CLK_32K>,
> +					 <&hdmi_tx_phy>;
> +				clock-names =3D "iahb", "isfr", "cec",=20
"pix";
> +				assigned-clocks =3D <&clk=20
IMX8MP_CLK_HDMI_REF_266M>;
> +				assigned-clock-parents =3D <&clk=20
IMX8MP_SYS_PLL1_266M>;
> +				power-domains =3D <&hdmi_blk_ctrl=20
IMX8MP_HDMIBLK_PD_HDMI_TX>;
> +				reg-io-width =3D <1>;
> +				status =3D "disabled";
> +
> +				ports {
> +					#address-cells =3D <1>;
> +					#size-cells =3D <0>;
> +
> +					port@0 {
> +						reg =3D <0>;
> +
> +						hdmi_tx_from_pvi:=20
endpoint {
> +							remote-
endpoint =3D <&pvi_to_hdmi_tx>;
> +						};
> +					};
> +
> +					port@1 {
> +						reg =3D <1>;
> +						/* Point endpoint=20
to the HDMI connector */
> +					};
> +				};
> +			};
> +
> +			hdmi_tx_phy: phy@32fdff00 {
> +				compatible =3D "fsl,imx8mp-hdmi-phy";
> +				reg =3D <0x32fdff00 0x100>;
> +				clocks =3D <&clk IMX8MP_CLK_HDMI_APB>,
> +					 <&clk IMX8MP_CLK_HDMI_24M>;
> +				clock-names =3D "apb", "ref";
> +				assigned-clocks =3D <&clk=20
IMX8MP_CLK_HDMI_24M>;
> +				assigned-clock-parents =3D <&clk=20
IMX8MP_CLK_24M>;
> +				power-domains =3D <&hdmi_blk_ctrl=20
IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
> +				#clock-cells =3D <0>;
> +				#phy-cells =3D <0>;
> +				status =3D "disabled";
> +			};

According to RM these blocks are part of AIPS4, so it should be below=20
hsio_blk_ctrl.

Best regards,
Alexander

>  		};
>=20
>  		aips5: bus@30c00000 {


=2D-=20
TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht M=FCnchen, HRB 105018
Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider
http://www.tq-group.com/