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From: Jingyi Wang <quic_jingyw@quicinc.com>
To: <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <andersson@kernel.org>,
        <konrad.dybcio@linaro.org>, <robh@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>
CC: <quic_jingyw@quicinc.com>, <kernel@quicinc.com>
Subject: [RFC PATCH 0/6] arm64: dts: qcom: Introduce AIM500 platform device tree
Date: Mon, 5 Feb 2024 19:57:15 +0800
Message-ID: <20240205115721.1195336-1-quic_jingyw@quicinc.com>
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Add the device tree for the AIM500 AIoT board along with usb, regulators,
serial and PCIe found in this board.

AIM500 Series is a highly optimized family of modules designed to support
AIoT and Generative AI applications which is based on SM8650P soc with
addtional functions like PMIC and bluetooth. And AIM500 AIoT is mounted
onto Qualcomm AIoT carrier board to support verification, evaluation and
development.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
---

This patch series has some open discussion topics depend on [1], including:
1. memory map will have a large reserved region for firmware related,
   since currently firmware features are still in developing and easily to
   be changed.
2. vph_pwr was open whether it should be put in som.dtsi, or board.dts. we
   can see vph_pwr may have different design and implementation from
   different boards design, while vph_pwr needed to be one of the som input,
   and then the vph_pwr is used inside som to different pmics input. So we
   proposed have the definition in som.dtsi, and have it's own implementation
   in board.dts.
3. board compatible like aim300-aiot was open whether can be added or not.
   We added currently since it will fail dt binding check if not.

[1] https://lore.kernel.org/linux-arm-msm/20240119100621.11788-1-quic_tengfan@quicinc.com/#t

And we got following error while doing dtb check:
sm8650p-aim500-aiot.dtb: usb@a6f8800: interrupt-names: ['hs_phy_irq', 'ss_phy_irq', 'dm_hs_phy_irq', 'dp_hs_phy_irq'] is too short
Which should be caused by missing intertupt name "pwr_event" in sm8650.dtsi

Jingyi Wang (6):
  dt-bindings: arm: qcom: Document sm8650p soc and AIM500 AIoT board
  dt-bindings: arm: qcom,ids: Add SoC ID for SM8650P
  soc: qcom: socinfo: Add SM8650P SoC ID table entry
  arm64: dts: qcom: sm8650p: introduce sm8650p dtsi
  arm64: dts: qcom: add base AIM500 dtsi
  arm64: dts: qcom: add AIM500 AIoT

 .../devicetree/bindings/arm/qcom.yaml         |   9 +
 arch/arm64/boot/dts/qcom/Makefile             |   1 +
 .../boot/dts/qcom/sm8650p-aim500-aiot.dts     | 314 ++++++++++++++
 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi  | 409 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/sm8650p.dtsi         | 180 ++++++++
 drivers/soc/qcom/socinfo.c                    |   1 +
 include/dt-bindings/arm/qcom,ids.h            |   1 +
 7 files changed, 915 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500-aiot.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sm8650p-aim500.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sm8650p.dtsi

--
base-commit: 076d56d74f17e625b3d63cf4743b3d7d02180379 
2.25.1