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Date: Tue, 6 Feb 2024 10:12:12 +0530
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Subject: Re: [PATCH 0/3] Add PCIe DT support for TI's J784S4 SoC
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To: Vignesh Raghavendra <vigneshr@ti.com>
References: <20240129114749.1197579-1-s-vadapalli@ti.com>
 <ffeb1902-332c-445b-a16a-7fc293cad2eb@ti.com>
From: Siddharth Vadapalli <s-vadapalli@ti.com>
In-Reply-To: <ffeb1902-332c-445b-a16a-7fc293cad2eb@ti.com>
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On 05/02/24 20:05, Vignesh Raghavendra wrote:
> 
> 
> On 29/01/24 17:17, Siddharth Vadapalli wrote:
>> Hello,
>>
>> TI's J784S4 SoC has two Gen3 x4 Lane PCIe Controllers. This series adds
>> the necessary device-tree support to enable both PCIe instances in Root
>> Complex mode of operation by default. The device-tree overlay to enable
>> both instances in Endpoint mode of operation is also present in this
>> series.
>>
>> **NOTE**
>> This series depends on:
>> 1. https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240124122936.816142-1-s-vadapalli@ti.com/
>>    for adding the Device ID in the bindings for J784S4 SoC.
>>
>> 2. https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240129104958.1139787-1-s-vadapalli@ti.com/
>>    for enabling support for configuring the PCIe mode of operation,
>>    number of lanes and link speed when the System Controller node
>>    in the device-tree is modelled as a "simple-bus" which happens to
>>    be the case for J784S4 SoC:
>>    https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi#L45
>>
>> 3. https://patchwork.kernel.org/project/linux-arm-kernel/patch/20240125100501.4137977-2-c-vankar@ti.com/
>>    for fixing the "serdes_ln_ctrl" node in order to ensure that the PCIe
>>    lanes are mapped correctly to the corresponding Serdes Lanes.
> 
> Sorry, too many dependencies for me to keep track of. I am ignoring  the
>  series, please resubmit once dependencies are resolved.

Sure Vignesh. I will post the v2 series once the dependencies are met.

-- 
Regards,
Siddharth.