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Subject: Re: [PATCHv1 3/5] arm64: dts: amlogic: Add cache information to the
 Amlogic G12A SoCS
From: Christian Hewitt <christianshewitt@gmail.com>
In-Reply-To: <4248e19e-5f2f-4e4f-a869-a0fec81b16bd@lexina.in>
Date: Tue, 6 Feb 2024 11:53:22 +0400
Cc: Rob Herring <robh+dt@kernel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 Conor Dooley <conor+dt@kernel.org>,
 Neil Armstrong <neil.armstrong@linaro.org>,
 Kevin Hilman <khilman@baylibre.com>,
 Jerome Brunet <jbrunet@baylibre.com>,
 Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
 devicetree <devicetree@vger.kernel.org>,
 linux-arm-kernel@lists.infradead.org,
 AML <linux-amlogic@lists.infradead.org>,
 LKML <linux-kernel@vger.kernel.org>,
 Viacheslav <adeep@lexina.in>
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Message-Id: <E850AF1E-BF7E-45F7-8AF0-68B548166094@gmail.com>
References: <20240205171930.968-1-linux.amoon@gmail.com>
 <20240205171930.968-4-linux.amoon@gmail.com>
 <4248e19e-5f2f-4e4f-a869-a0fec81b16bd@lexina.in>
To: Anand Moon <linux.amoon@gmail.com>

> On 6 Feb 2024, at 11:48=E2=80=AFam, Viacheslav <adeep@lexina.in> =
wrote:
>=20
> You missed the AXG family with the Cortex-A53 CPU. The datasheet does =
not provide information on cache sizes. Given that the A113X/A113D are =
equipped with the Arm Cortex-A53 processor, it is assumed they use the =
same cache size as the S905/S905X/S905X2 models.

GXM is also missing, and also using A53 cores.

Christian

> 05/02/2024 20.19, Anand Moon wrote:
>> As per the S905X2 datasheet add missing cache information to the =
Amlogic
>> G12A SoC.
>> - Each Cortex-A53 core has 32KB of L1 instruction cache available and
>> 32KB of L1 data cache available.
>> - Along with 512KB Unified L2 cache.
>> To improve system performance.
>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>> ---
>> No public dataheet available, since S905X2 support Arm Cortex-A53 cpu
>> nence used the same cache size as S905 and S905X.
>> ---
>>  arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 =
+++++++++++++++++++++
>>  1 file changed, 27 insertions(+)
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi =
b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> index 543e70669df5..6e1e3a3f5f18 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> @@ -17,6 +17,12 @@ cpu0: cpu@0 {
>>   compatible =3D "arm,cortex-a53";
>>   reg =3D <0x0 0x0>;
>>   enable-method =3D "psci";
>> + d-cache-line-size =3D <32>;
>> + d-cache-size =3D <0x8000>;
>> + d-cache-sets =3D <32>;
>> + i-cache-line-size =3D <32>;
>> + i-cache-size =3D <0x8000>;
>> + i-cache-sets =3D <32>;
>>   next-level-cache =3D <&l2>;
>>   #cooling-cells =3D <2>;
>>   };
>> @@ -26,6 +32,12 @@ cpu1: cpu@1 {
>>   compatible =3D "arm,cortex-a53";
>>   reg =3D <0x0 0x1>;
>>   enable-method =3D "psci";
>> + d-cache-line-size =3D <32>;
>> + d-cache-size =3D <0x8000>;
>> + d-cache-sets =3D <32>;
>> + i-cache-line-size =3D <32>;
>> + i-cache-size =3D <0x8000>;
>> + i-cache-sets =3D <32>;
>>   next-level-cache =3D <&l2>;
>>   #cooling-cells =3D <2>;
>>   };
>> @@ -35,6 +47,12 @@ cpu2: cpu@2 {
>>   compatible =3D "arm,cortex-a53";
>>   reg =3D <0x0 0x2>;
>>   enable-method =3D "psci";
>> + d-cache-line-size =3D <32>;
>> + d-cache-size =3D <0x8000>;
>> + d-cache-sets =3D <32>;
>> + i-cache-line-size =3D <32>;
>> + i-cache-size =3D <0x8000>;
>> + i-cache-sets =3D <32>;
>>   next-level-cache =3D <&l2>;
>>   #cooling-cells =3D <2>;
>>   };
>> @@ -44,6 +62,12 @@ cpu3: cpu@3 {
>>   compatible =3D "arm,cortex-a53";
>>   reg =3D <0x0 0x3>;
>>   enable-method =3D "psci";
>> + d-cache-line-size =3D <32>;
>> + d-cache-size =3D <0x8000>;
>> + d-cache-sets =3D <32>;
>> + i-cache-line-size =3D <32>;
>> + i-cache-size =3D <0x8000>;
>> + i-cache-sets =3D <32>;
>>   next-level-cache =3D <&l2>;
>>   #cooling-cells =3D <2>;
>>   };
>> @@ -52,6 +76,9 @@ l2: l2-cache0 {
>>   compatible =3D "cache";
>>   cache-level =3D <2>;
>>   cache-unified;
>> + cache-size =3D <0x7d000>; /* L2. 512 KB */
>> + cache-line-size =3D <64>;
>> + cache-sets =3D <512>;
>>   };
>>   };
>> =20
>=20
>=20
> Best regards,
> --
> Viacheslav Bocharov <adeep@lexina.in>
>=20
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