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Date: Tue, 6 Feb 2024 11:29:31 +0000
From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Hojin Nam <hj96.nam@samsung.com>
CC: "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>, Wonjae Lee
	<wj28.lee@samsung.com>, KyungSan Kim <ks0204.kim@samsung.com>,
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	<linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>, "will@kernel.org" <will@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>
Subject: Re: [PATCH] perf: CXL: fix mismatched cpmu event opcode
Message-ID: <20240206112931.00004224@Huawei.com>
In-Reply-To: <20240206102132.00000797@Huawei.com>
References: <CGME20240206094151epcms2p373ed7f50efa332765e14bff2b5a2abe2@epcms2p3>
	<20240206094151epcms2p373ed7f50efa332765e14bff2b5a2abe2@epcms2p3>
	<20240206102132.00000797@Huawei.com>
Organization: Huawei Technologies Research and Development (UK) Ltd.
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On Tue, 6 Feb 2024 10:21:32 +0000
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:

> On Tue, 06 Feb 2024 18:41:51 +0900
> Hojin Nam <hj96.nam@samsung.com> wrote:
> 
> > S2M NDR BI-ConflictAck opcode is described as 4 in the CXL
> > 3.0 specification. However, it is defined as 3 in macro definition.
> >   
> Please provide a reference to a specific spec section.
> Ideally from r3.1 as that's the easily available version today.
> I think this is Table 3-50 S2M NDR Opcodes in r3.1
> 
> Looks like s2m_ndr_cmpm should be there for bit 3 so we should probably
> add that as part of the fix.
> 
Also, please add a Fixes tag.
> 
> > Signed-off-by: Hojin Nam <hj96.nam@samsung.com>
> > ---
> >  drivers/perf/cxl_pmu.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
> > index 365d964b0f6a..bc0d414a6aff 100644
> > --- a/drivers/perf/cxl_pmu.c
> > +++ b/drivers/perf/cxl_pmu.c
> > @@ -419,7 +419,7 @@ static struct attribute *cxl_pmu_event_attrs[] = {
> >         CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmp,                     CXL_PMU_GID_S2M_NDR, BIT(0)),
> >         CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmps,                    CXL_PMU_GID_S2M_NDR, BIT(1)),
> >         CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_cmpe,                    CXL_PMU_GID_S2M_NDR, BIT(2)),
> > -       CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack,           CXL_PMU_GID_S2M_NDR, BIT(3)),
> > +       CXL_PMU_EVENT_CXL_ATTR(s2m_ndr_biconflictack,           CXL_PMU_GID_S2M_NDR, BIT(4)),
> >         /* CXL rev 3.0 Table 3-46 S2M DRS opcodes */
> >         CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdata,                 CXL_PMU_GID_S2M_DRS, BIT(0)),
> >         CXL_PMU_EVENT_CXL_ATTR(s2m_drs_memdatanxm,              CXL_PMU_GID_S2M_DRS, BIT(1)),
> > --
> > 2.34.1  
> 
>