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From: Conor Dooley <conor@kernel.org>
To: linux-riscv@lists.infradead.org,
	Conor Dooley <conor@kernel.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
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Subject: Re: (subset) [PATCH v2 0/7] MPFS clock fixes required for correct CAN clock modeling
Date: Tue,  6 Feb 2024 14:27:31 +0000
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From: Conor Dooley <conor.dooley@microchip.com>

On Mon, 22 Jan 2024 12:19:48 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> While reviewing a CAN driver internally for MPFS [1], I realised
> that the modeling of the MSSPLL such that only one of its outputs could
> be used was not correct. The CAN controllers on MPFS take 2 input
> clocks - one that is the bus clock, acquired from the main MSSPLL and
> a second clock for the AHB interface to the result of the SoC.
> Currently the binding for the CAN controllers and the represetnation
> of the MSSPLL only allows for one of these clocks.
> Modify the binding and devicetree to expect two clocks and rework the
> main clock controller driver for MPFS such that it is capable of
> providing multiple outputs from the MSSPLL.
> 
> [...]

And this one is applied to riscv-dt-for-next. I don't think sending this
for the -rcs is needed as there's no impact until the CAN driver shows up.

[7/7] riscv: dts: microchip: add missing CAN bus clocks
      https://git.kernel.org/conor/c/6c7353836a91

Thanks,
Conor.