Received-SPF: pass (google.com: domain of linux-kernel+bounces-55239-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
Date: Tue, 6 Feb 2024 10:24:42 -0500
From: Frank Li <Frank.li@nxp.com>
To: Shawn Guo <shawnguo2@yeah.net>
Cc: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" <linux-arm-kernel@lists.infradead.org>,
	open list <linux-kernel@vger.kernel.org>, imx@lists.linux.dev
Subject: Re: [PATCH 2/2] arm64: dts: imx8dxl update edma0 information
Message-ID: <ZcJPOldJBIo3E7RK@lizhi-Precision-Tower-5810>
References: <20240129201633.234255-1-Frank.Li@nxp.com>
 <20240129201633.234255-2-Frank.Li@nxp.com>
 <ZcIMJWKBrPW4Y5R8@dragon>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <ZcIMJWKBrPW4Y5R8@dragon>
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?k6O9aqvuZscFd9itcNjJjCQYP2mNRIDa+b284s+SlTPBdSQSQP64tZmQpsew?=
 =?us-ascii?Q?/JiArq1Tc3WAxv9vUctzWaxcYqVubsywmNDvo9nxv8NcMBlMXWvv3Ls/vfzM?=
 =?us-ascii?Q?s40DoYSdw086pe5/Otm9zAX5rs5NFu0CkSzr2jnSCYh+sf1lcG1KVzg5ijou?=
 =?us-ascii?Q?nDGzsME7Jvk/6si5qDkMWf1ZQxe/38KL+YKdq/JQdIiUPNzaB7fqoy9yxQM8?=
 =?us-ascii?Q?uxzTJLNtSzPK3tmSXiAa/jllm2H+cS/Z17+f/OtQHJ74L4NQ27mw8ATcUTug?=
 =?us-ascii?Q?5B8uLrGN1Ib/DvIB35hM3bP7WgN576vwdSyL4h9G63PsxYhkGAPOKEJ3flKm?=
 =?us-ascii?Q?qmgVY0F4yDGaDnAEdJzgMyzFTMK1l9bd64hluVmML1T14HKlpYwzHIAYTLnc?=
 =?us-ascii?Q?hSQXSh5Dz7N5YYUXgEDz/p2y2MIOUr8sUYapGEl4sWMvhKGPa4IP+DJ5okd/?=
 =?us-ascii?Q?wWCJcEWLAfLcc7Mhcz9hplVCo+4qKe8vra21CkigEC9u+dvwgNT0Mi75XvMW?=
 =?us-ascii?Q?i+X+xLikMkE4kQjwe92TMVQH8viYYB5CWupR6CMfq6wmA8i9kxaN4zQ7VlIW?=
 =?us-ascii?Q?ISRfqtxdnuaA6XLpYtsr+Kwim7/L8fO4DKGujYf7HAdE4AzDKP66906wvEUF?=
 =?us-ascii?Q?6DcymvAbL1dAmqy+0a5O6DvXGfuVQRgutKykLjppoc3wIZKjZmDaHH3eqbU+?=
 =?us-ascii?Q?R9YNZJ086q1M6Ljy8U/zCPHH6l1hHqX4FhjOUDrWbcOwoEGbUOr6KNRiAT6f?=
 =?us-ascii?Q?Mylj7lXAvorFytf4VX2Bf+jNAI3lOhGf2jmgIqOO2JvSkZXJiCGe6mW3nyEU?=
 =?us-ascii?Q?24o5zqsmpXp4DeUofLovTmJTIc9hmnHJsRp0SXmFXEpIFRZWuctszZx5Spw9?=
 =?us-ascii?Q?zN6rjlhmMtWYATFW4snE2qhhFgEWZ2OW5dVXETEqEuPC7G3iqMBPbYmwbvKM?=
 =?us-ascii?Q?HNZkqSgxftYgiw6Rm3qpdSMdsv/f2cc+s9XZMAvPfLCxxX4/sRppwya59Goj?=
 =?us-ascii?Q?KuXZBk15FdhbEdtBSeHsvntB5nQhG/6s6HBQesBW7e1W+lrhomKg7gNISzH5?=
 =?us-ascii?Q?XTujplWSVhgdakxlUY6fbVSJfg8ig92bUMVZj4htEUJ0LWDiSqWTsvL+5Swl?=
 =?us-ascii?Q?0Xloot5okOX2XF4YuL0FqAipsEsztMSw1kFBltQe8ZaKg5d8DTm//iJbG7sx?=
 =?us-ascii?Q?6cV2n2sggeOOllGjBQmFKZtdaXB+fUDbqIRly+9fbWFvFpNf1o1qPJR0ivCM?=
 =?us-ascii?Q?XCDlg5wZFPAVBXtVb7hIujlGmP2r4db/yPvjbiusIVbrudVTXqUbhCtcmsjE?=
 =?us-ascii?Q?MOc61l5LTfsY7P1DHQ9NRYIOjsCo8YkF6ufgg6VxvAsWL1HI1epjHIn2b2ZI?=
 =?us-ascii?Q?PVc5svQrzSfPxpr8axZ+h0Mf+xCqqeFDDgB4kaLgpAoaJ+QWp9VL3WSjO3T7?=
 =?us-ascii?Q?fWJf9xf4+p12Gq5tnvenwGhR4v+KvaQpTHE90Wxcx8Ks62DxAKlWSZT3sCRC?=
 =?us-ascii?Q?X2D+n++zvT2dv/n4zz/tAiT+ZU1N8ft3JZts5VbKhx5SFm/ew7aXaCOyJbFT?=
 =?us-ascii?Q?RXLyh1FodfzWH5yWF0o0JPKHVBR/8eeFV7VY04J7?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: ff027dcc-55ae-480e-c088-08dc2727c25b
X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2024 15:24:49.9475
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: L2oIxTqHQaBPJuOkN559qlPhTR7k/ARHP0pNDQjY9XgNvD4P2R5xXIXpwL9eoG+/fk5GanXEGW22z4rob5GG6Q==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR04MB9439

On Tue, Feb 06, 2024 at 06:38:29PM +0800, Shawn Guo wrote:
> On Mon, Jan 29, 2024 at 03:16:32PM -0500, Frank Li wrote:
> > edma0 of iMX8DXL is difference with other imx8 chips. Update register's
> > size, channel number and power-domain.
> > Update i2c[0-3] channel number information.
> > 
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   | 65 +++++++++++++++++++
> >  1 file changed, 65 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > index 0a477f6318f15..f8fca86babda7 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > @@ -15,6 +15,63 @@ &adc0 {
> >  	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> >  };
> >  
> > +&edma0 {
> > +	reg = <0x591f0000 0x1a0000>;
> > +	#dma-cells = <3>;
> > +	dma-channels = <25>;
> > +	dma-channel-mask = <0x1c0cc0>;
> > +	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
> > +		<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
> > +		<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
> > +		<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
> > +		<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
> > +		<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */
> > +		<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */
> > +		<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */
> > +		<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */
> > +	power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
> > +			<&pd IMX_SC_R_DMA_0_CH1>,
> > +			<&pd IMX_SC_R_DMA_0_CH2>,
> > +			<&pd IMX_SC_R_DMA_0_CH3>,
> > +			<&pd IMX_SC_R_DMA_0_CH4>,
> > +			<&pd IMX_SC_R_DMA_0_CH5>,
> > +			<&pd IMX_SC_R_DMA_0_CH6>,
> > +			<&pd IMX_SC_R_DMA_0_CH7>,
> > +			<&pd IMX_SC_R_DMA_0_CH8>,
> > +			<&pd IMX_SC_R_DMA_0_CH9>,
> > +			<&pd IMX_SC_R_DMA_0_CH10>,
> > +			<&pd IMX_SC_R_DMA_0_CH11>,
> > +			<&pd IMX_SC_R_DMA_0_CH12>,
> > +			<&pd IMX_SC_R_DMA_0_CH13>,
> > +			<&pd IMX_SC_R_DMA_0_CH14>,
> > +			<&pd IMX_SC_R_DMA_0_CH15>,
> > +			<&pd IMX_SC_R_DMA_0_CH16>,
> > +			<&pd IMX_SC_R_DMA_0_CH17>,
> > +			<&pd IMX_SC_R_DMA_0_CH18>,
> > +			<&pd IMX_SC_R_DMA_0_CH19>,
> > +			<&pd IMX_SC_R_DMA_0_CH20>,
> > +			<&pd IMX_SC_R_DMA_0_CH21>,
> > +			<&pd IMX_SC_R_DMA_0_CH22>,
> > +			<&pd IMX_SC_R_DMA_0_CH23>,
> > +			<&pd IMX_SC_R_DMA_0_CH24>;
> > +};
> > +
> >  &edma2 {
> >  	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
> >  		     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> > @@ -48,21 +105,29 @@ &edma3 {
> >  &i2c0 {
> >  	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
> >  	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> > +	dma-names = "tx","rx";
> > +	dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>;
> >  };
> >  
> >  &i2c1 {
> >  	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
> >  	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> > +	dma-names = "tx","rx";
> > +	dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>;
> 
> No FSL_EDMA_TX for "tx"?

Yes, only defined FSL_EDMA_RX. It is bitmask. If no FSL_EDMA_RX, means
TX channel.

Frank

> 
> Shawn
> 
> >  };
> >  
> >  &i2c2 {
> >  	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
> >  	interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> > +	dma-names = "tx","rx";
> > +	dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>;
> >  };
> >  
> >  &i2c3 {
> >  	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
> >  	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> > +	dma-names = "tx","rx";
> > +	dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>;
> >  };
> >  
> >  &lpuart0 {
> > -- 
> > 2.34.1
> > 
>