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Message-ID: <b5b70049-81f6-455e-b2bf-d03431e5b27b@ti.com>
Date: Tue, 6 Feb 2024 12:50:38 -0600
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Subject: Re: [PATCH v1] arm64: dts: ti: verdin-am62: mallow: add TPM device
Content-Language: en-US
To: Francesco Dolcini <francesco@dolcini.it>, Nishanth Menon <nm@ti.com>,
        Vignesh Raghavendra <vigneshr@ti.com>, Tero Kristo <kristo@kernel.org>,
        Rob
 Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>
CC: Francesco Dolcini <francesco.dolcini@toradex.com>,
        <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
References: <20240126165136.28543-1-francesco@dolcini.it>
 <65a24f21-4cc6-4843-b838-b1c7020ca45d@ti.com>
 <26F9C286-606C-40C6-994E-EABDFFCDFDC4@dolcini.it>
From: Andrew Davis <afd@ti.com>
In-Reply-To: <26F9C286-606C-40C6-994E-EABDFFCDFDC4@dolcini.it>
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On 2/6/24 12:36 PM, Francesco Dolcini wrote:
> 
> 
> Il 6 febbraio 2024 19:29:13 CET, Andrew Davis <afd@ti.com> ha scritto:
>> On 1/26/24 10:51 AM, Francesco Dolcini wrote:
>>> From: Francesco Dolcini <francesco.dolcini@toradex.com>
>>>
>>> Add TPM device to Mallow device tree file, the device is connected to
>>> the SoC with SPI1/CS1, the same SPI interface is also available on an
>>> extension header together with an additional CS0 signal.
>>>
>>> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
>>> ---
>>>    arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi | 10 ++++++++++
>>>    1 file changed, 10 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi
>>> index 17b93534f658..77b1beb638ad 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi
>>> @@ -127,6 +127,16 @@ &main_spi1 {
>>>    		    <&pinctrl_qspi1_cs2_gpio>;
>>>    	cs-gpios = <0>, <&main_gpio0 12 GPIO_ACTIVE_LOW>;
>>>    	status = "okay";
>>> +
>>> +	tpm@1 {
>>> +		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
>>> +		reg = <1>;
>>> +		pinctrl-names = "default";
>>> +		pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>;
>>> +		interrupt-parent = <&main_gpio1>;
>>> +		interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
>>
>> Just a heads-up, the SLB9670 datasheet says this device uses
>> an active low interrupt (IRQ_TYPE_LEVEL_LOW). Using TYPE_EDGE
>> here can cause missed interrupts if the line stays low for
>> multiple interrupts.
> 
> 
> The driver interrupt handler would need to take care of it, if needed.
> 
> The SOC does not support level interrupt, so there is no other solution, am I wrong?

Correct, our K3 SoCs do not support level interrupts and so are not compatible
with most hardware that uses interrupts (unless you are okay with missing
some interrupts every now and then..).

As you say, our interrupt driver needs to be modified to handle that. Possibly
by re-checking the line level after the interrupt handlers have all run to see
if it is still high/low, then manually re-triggering the interrupt if so.

The heads-up is just that you should be aware of this in case you have issues.
When(if) our interrupt driver is ever fixed you will need to update the DT here
to take advantage of the level handler.

Andrew

>   
> Francesco
>