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Message-ID: <9cfc65c594deef33f24b60a66b7c78c742da7203.camel@linux.intel.com>
Subject: Re: [PATCH v2] PCI: vmd: Enable PCI PM's L1 substates of remapped
 PCIe Root Port and NVMe
From: "David E. Box" <david.e.box@linux.intel.com>
Reply-To: david.e.box@linux.intel.com
To: Bjorn Helgaas <helgaas@kernel.org>, puranjay12@gmail.com
Cc: Jian-Hong Pan <jhp@endlessos.org>, Johan Hovold <johan@kernel.org>, Mika
 Westerberg <mika.westerberg@linux.intel.com>, Damien Le Moal
 <dlemoal@kernel.org>, Niklas Cassel <cassel@kernel.org>, Nirmal Patel
 <nirmal.patel@linux.intel.com>, Jonathan Derrick
 <jonathan.derrick@linux.dev>, linux-pci@vger.kernel.org,
 linux-kernel@vger.kernel.org,  linux@endlessos.org
Date: Tue, 06 Feb 2024 13:25:29 -0800
In-Reply-To: <02938148545933dc9865ddbc5551e3e8a579d57e.camel@linux.intel.com>
References: <20240205224215.GA829734@bhelgaas>
	 <02938148545933dc9865ddbc5551e3e8a579d57e.camel@linux.intel.com>
Organization: David E. Box
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Adding Puranjay

On Mon, 2024-02-05 at 15:05 -0800, David E. Box wrote:
> On Mon, 2024-02-05 at 16:42 -0600, Bjorn Helgaas wrote:
> > On Mon, Feb 05, 2024 at 11:37:16AM -0800, David E. Box wrote:
> > > On Fri, 2024-02-02 at 18:05 -0600, Bjorn Helgaas wrote:
> > > > On Fri, Feb 02, 2024 at 03:11:12PM +0800, Jian-Hong Pan wrote:
> > > ...
> >=20
> > > > > @@ -775,6 +773,14 @@ static int vmd_pm_enable_quirk(struct pci_de=
v
> > > > > *pdev,
> > > > > void *userdata)
> > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pci_write_config_=
dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT,
> > > > > ltr_reg);
> > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0pci_info(pdev, "V=
MD: Default LTR value set by driver\n");
> > > >=20
> > > > You're not changing this part, and I don't understand exactly how L=
TR
> > > > works, but it makes me a little bit queasy to read "set the LTR val=
ue
> > > > to the maximum required to allow the deepest power management
> > > > savings" and then we set the max snoop values to a fixed constant.
> > > >=20
> > > > I don't think the goal is to "allow the deepest power savings"; I
> > > > think it's to enable L1.2 *when the device has enough buffering to
> > > > absorb L1.2 entry/exit latencies*.
> > > >=20
> > > > The spec (PCIe r6.0, sec 7.8.2.2) says "Software should set this to
> > > > the platform's maximum supported latency or less," so it seems like
> > > > that value must be platform-dependent, not fixed.
> > > >=20
> > > > And I assume the "_DSM for Latency Tolerance Reporting" is part of =
the
> > > > way to get those platform-dependent values, but Linux doesn't actua=
lly
> > > > use that yet.
> > >=20
> > > This may indeed be the best way but we need to double check with our
> > > BIOS folks.=C2=A0 AFAIK BIOS writes the LTR values directly so there
> > > hasn't been a need to use this _DSM. But under VMD the ports are
> > > hidden from BIOS which is why we added it here. I've brought up the
> > > question internally to find out how Windows handles the DSM and to
> > > get a recommendation from our firmware leads.
> >=20
> > We want Linux to be able to program LTR itself, don't we?=C2=A0 We
> > shouldn't have to rely on firmware to do it.=C2=A0 If Linux can't do
> > it, hot-added devices aren't going to be able to use L1.2, right?
>=20
> Agreed. We just want to make sure we are not conflicting with what BIOS m=
ay be
> doing.

So the feedback is to run the _DSM and just overwrite any BIOS values. Look=
ing
up the _DSM I saw there was an attempt to upstream this 4 years ago [1]. I'=
m not
sure why the effort stalled but we can pick up this work again.

https://patchwork.kernel.org/project/linux-pci/patch/20201015080311.7811-1-=
puranjay12@gmail.com/