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AJvYcCWgHbZftWk+USKPzl2FUBQfarKgc3/l2vQb9rLjNJ9WlJdBxoznVZiBIXRNP3KtSr4PdO64FdE9yw6elJg/snrbyAqfcr7gA4CWgpqv X-Gm-Message-State: AOJu0YwPQRs5dzloHXbL247rZ7JlMJR7KKao2VZxYtXLtNeghXauJ+3I +3dzCEYlMq4AYg/RcY516Cm+2HTImc8kJLLkUQpi7zqm+YaHlPM6+SrkWmr3ksFlzkxk5Qx8aV7 uUU1SZcdydXjmtOMjbv2RM762IyfphIxKxwFaFg== X-Received: by 2002:a81:a193:0:b0:5ff:6028:99f5 with SMTP id y141-20020a81a193000000b005ff602899f5mr3377783ywg.41.1707269533799; Tue, 06 Feb 2024 17:32:13 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240206114745.1388491-1-quic_kriskura@quicinc.com> <20240206114745.1388491-4-quic_kriskura@quicinc.com> <23824242-1b37-4544-ae9a-0a5a0582580e@linaro.org> <6q2ocvrujbli42rjddflyol74xianr7j47jwcgdnnmwjanv25d@uw2da7zulqqd> In-Reply-To: <6q2ocvrujbli42rjddflyol74xianr7j47jwcgdnnmwjanv25d@uw2da7zulqqd> From: Dmitry Baryshkov Date: Wed, 7 Feb 2024 03:32:03 +0200 Message-ID: Subject: Re: Re: [PATCH 3/3] arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller To: Andrew Halaney Cc: neil.armstrong@linaro.org, Krishna Kurapati , Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Konrad Dybcio , Conor Dooley , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, quic_ppratap@quicinc.com, quic_jackp@quicinc.com Content-Type: text/plain; charset="UTF-8" On Wed, 7 Feb 2024 at 02:10, Andrew Halaney wrote: > > On Tue, Feb 06, 2024 at 03:30:32PM +0200, Dmitry Baryshkov wrote: > > On Tue, 6 Feb 2024 at 15:28, wrote: > > > > > > On 06/02/2024 12:47, Krishna Kurapati wrote: > > > > From: Andrew Halaney > > > > > > > > There is now support for the multiport USB controller this uses so > > > > enable it. > > > > > > > > The board only has a single port hooked up (despite it being wired up to > > > > the multiport IP on the SoC). There's also a USB 2.0 mux hooked up, > > > > which by default on boot is selected to mux properly. Grab the gpio > > > > controlling that and ensure it stays in the right position so USB 2.0 > > > > continues to be routed from the external port to the SoC. > > > > What is connected to the other port of the MUX? > > /me blows off the dust on the schematic > > It's a 1:2 mux, and one option is the out the board, the other > is a test point I believe if I'm reading things right, although its not > labeled so I'm not sure anyone would actually find it on the board. Ack, this definitely looks like a static configuration. > > > > > > > > > > > Signed-off-by: Andrew Halaney > > > > Co-developed-by: Krishna Kurapati > > > > Signed-off-by: Krishna Kurapati > > > > --- > > > > arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 21 +++++++++++++++++++++ > > > > 1 file changed, 21 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > > > > index b04f72ec097c..eed1ddc29bc1 100644 > > > > --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > > > > +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts > > > > @@ -503,6 +503,18 @@ &usb_2_qmpphy0 { > > > > status = "okay"; > > > > }; > > > > > > > > +&usb_2 { > > > > + pinctrl-0 = <&usb2_en>; > > > > + pinctrl-names = "default"; > > > > + > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&usb_2_dwc3 { > > > > + phy-names = "usb2-port0", "usb3-port0"; > > > > + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>; > > > > +}; > > > > + > > > > &xo_board_clk { > > > > clock-frequency = <38400000>; > > > > }; > > > > @@ -655,4 +667,13 @@ wake-pins { > > > > bias-pull-up; > > > > }; > > > > }; > > > > + > > > > + usb2_en: usb2-en-state { > > > > + /* TS3USB221A USB2.0 mux select */ > > > > + pins = "gpio24"; > > > > + function = "gpio"; > > > > + drive-strength = <2>; > > > > + bias-disable; > > > > + output-low; > > > > + }; > > > > }; > > > > > > Isn't gpio-hog the preferred way to describe that ? > > > > That depends. As this pinctrl describes board configuration, I'd agree > > with Neil. > > I unfortunately don't have the experience with gpio-hog to weigh in > here, but wouldn't be opposed to Krishna switching it if that's what's > recommended for this type of thing. Quoting gpio.txt: The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism providing automatic GPIO request and configuration as part of the gpio-controller's driver probe function. See sdm845-pinctrl.yaml for an example of the gpio-hog node. > > > > > > > -- > > With best wishes > > Dmitry > > > -- With best wishes Dmitry