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From: Thomas Gleixner <tglx@linutronix.de>
To: Marcelo Tosatti <mtosatti@redhat.com>, linux-kernel@vger.kernel.org
Cc: Daniel Bristot de Oliveira <bristot@kernel.org>, Juri Lelli
 <juri.lelli@redhat.com>, Valentin Schneider <vschneid@redhat.com>,
 Frederic Weisbecker <frederic@kernel.org>, Leonardo Bras
 <leobras@redhat.com>, Peter Zijlstra <peterz@infradead.org>, Marcelo
 Tosatti <mtosatti@redhat.com>
Subject: Re: [patch 12/12] x86/cacheinfo.c: check for block interference CPUs
In-Reply-To: <20240206185710.142514323@redhat.com>
References: <20240206184911.248214633@redhat.com>
 <20240206185710.142514323@redhat.com>
Date: Wed, 07 Feb 2024 13:41:36 +0100
Message-ID: <87eddomoov.ffs@tglx>
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain

On Tue, Feb 06 2024 at 15:49, Marcelo Tosatti wrote:
> @@ -396,6 +397,7 @@ static void amd_l3_disable_index(struct
>  	 *  disable index in all 4 subcaches
>  	 */
>  	for (i = 0; i < 4; i++) {
> +		int ret;
>  		u32 reg = idx | (i << 20);
>  
>  		if (!nb->l3_cache.subcaches[i])
> @@ -409,6 +411,7 @@ static void amd_l3_disable_index(struct
>  		 * is not sufficient.
>  		 */
>  		ret = wbinvd_on_cpu(cpu);
> +		WARN_ON(ret == -EPERM);

What? You create inconsistent state here.

> -	amd_l3_disable_index(nb, cpu, slot, index);
> +	ret = 0;
> +	idx = block_interf_srcu_read_lock();
> +
> +	if (block_interf_cpu(cpu))
> +		ret = -EPERM;
> +	else
> +		amd_l3_disable_index(nb, cpu, slot, index);
> +
> +	block_interf_srcu_read_unlock(idx);

Again. This is a root only operation.

This whole patch series is just voodoo programming with zero
justification for the mess it creates.

Thanks,

        tglx
.