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Wed, 07 Feb 2024 05:10:52 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240127161753.114685-1-apatel@ventanamicro.com> <87h6ily53k.fsf@all.your.base.are.belong.to.us> <874jekag3w.fsf@all.your.base.are.belong.to.us> <87plx8y5s3.fsf@all.your.base.are.belong.to.us> <87sf24mo1g.fsf@all.your.base.are.belong.to.us> In-Reply-To: <87sf24mo1g.fsf@all.your.base.are.belong.to.us> From: Anup Patel Date: Wed, 7 Feb 2024 18:40:40 +0530 Message-ID: Subject: Re: [PATCH v12 00/25] Linux RISC-V AIA Support To: =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley , devicetree@vger.kernel.org, Saravana Kannan , Marc Zyngier , linux-kernel@vger.kernel.org, Atish Patra , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Andrew Jones Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Feb 7, 2024 at 6:25=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel wrote: > > Bj=C3=B6rn T=C3=B6pel writes: > > >>> Hmm, seems like we're talking past each other, or at least I get the > >>> feeling I can't get my opinions out right. I'll try to do a quick PoC= , > >>> to show you what I mean. That's probably easier than just talking abo= ut > >>> it. ...and maybe I'll come realizing I'm all wrong! > >> > >> I suggest to wait for my v13 and try something on top of that > >> otherwise we might duplicate efforts. > > > > OK! > > I did some really rough code sketching, and I'm confident that you can > get rid of all ids_enabled_bitmap, hwirqs_used_bitmap, and the > corresponding functions/locks. I'd say one lock is enough, and the key > is having the per-cpu imsic_local_priv.vectors change from struct > imsic_vector * to struct imsic_vector **. > > Using smp_call_function_single() to IPI enable (and disable if you don't > want to use the lazy timer disable mechanism) seems feasible as well! > > (Let me know if you don't have the spare cycles, and I can help out.) If you can help upstream IOMMU driver then that would be awesome. Regards, Anup