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From: "Akula, Kalyani" <kalyani.akula@amd.com>
To: "Kundanala, Praveen Teja" <praveen.teja.kundanala@amd.com>,
	"srinivas.kandagatla@linaro.org" <srinivas.kandagatla@linaro.org>, "Simek,
 Michal" <michal.simek@amd.com>, "Kundanala, Praveen Teja"
	<praveen.teja.kundanala@amd.com>, "devicetree@vger.kernel.org"
	<devicetree@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
CC: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH V4 3/4] nvmem: zynqmp_nvmem: Add support to access efuse
Thread-Topic: [PATCH V4 3/4] nvmem: zynqmp_nvmem: Add support to access efuse
Thread-Index: AQHaVcyGu1zT8gGX0EiQTXcAtXl0ULEACgvQ
Date: Thu, 8 Feb 2024 06:48:36 +0000
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>-----Original Message-----
>From: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
>Sent: Friday, February 2, 2024 5:09 PM
>To: srinivas.kandagatla@linaro.org; Simek, Michal <michal.simek@amd.com>;
>Akula, Kalyani <kalyani.akula@amd.com>; Kundanala, Praveen Teja
><praveen.teja.kundanala@amd.com>; devicetree@vger.kernel.org; linux-arm-
>kernel@lists.infradead.org
>Cc: linux-kernel@vger.kernel.org
>Subject: [PATCH V4 3/4] nvmem: zynqmp_nvmem: Add support to access efuse
>
>Add support to read/write efuse memory map of ZynqMP.
>Below are the offsets of ZynqMP efuse memory map
>	0 - SOC version(read only)
>	0xC - 0xFC -ZynqMP specific purpose efuses
>	0x100 - 0x17F - Physical Unclonable Function(PUF)
>                efuses repurposed as user efuses
>
>Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com>
>---
> drivers/nvmem/zynqmp_nvmem.c | 186
>+++++++++++++++++++++++++++++++++--
> 1 file changed, 176 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/nvmem/zynqmp_nvmem.c
>b/drivers/nvmem/zynqmp_nvmem.c index 391d8e88b270..8682adaacd69
>100644
>--- a/drivers/nvmem/zynqmp_nvmem.c
>+++ b/drivers/nvmem/zynqmp_nvmem.c
>@@ -4,6 +4,7 @@
>  * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
>  */
>
>+#include <linux/dma-mapping.h>
> #include <linux/module.h>
> #include <linux/nvmem-provider.h>
> #include <linux/of.h>
>@@ -11,24 +12,189 @@
> #include <linux/firmware/xlnx-zynqmp.h>
>
> #define SILICON_REVISION_MASK 0xF
>+#define P_USER_0_64_UPPER_MASK	GENMASK(31, 16)
>+#define P_USER_127_LOWER_4_BIT_MASK GENMASK(3, 0)
>+#define WORD_INBYTES		4
>+#define SOC_VER_SIZE		0x4
>+#define EFUSE_MEMORY_SIZE	0x177
>+#define UNUSED_SPACE		0x8
>+#define ZYNQMP_NVMEM_SIZE	(SOC_VER_SIZE + UNUSED_SPACE + \
>+				 EFUSE_MEMORY_SIZE)
>+#define SOC_VERSION_OFFSET	0x0
>+#define EFUSE_START_OFFSET	0xC
>+#define EFUSE_END_OFFSET	0xFC
>+#define EFUSE_PUF_START_OFFSET	0x100
>+#define EFUSE_PUF_MID_OFFSET	0x140
>+#define EFUSE_PUF_END_OFFSET	0x17F
>+#define EFUSE_NOT_ENABLED	29
>
>+/*
>+ * efuse access type
>+ */
>+enum efuse_access {
>+	EFUSE_READ =3D 0,
>+	EFUSE_WRITE
>+};
>+
>+/**
>+ * struct xilinx_efuse - the basic structure
>+ * @src:	address of the buffer to store the data to be write/read
>+ * @size:	read/write word count
>+ * @offset:	read/write offset
>+ * @flag:	0 - represents efuse read and 1- represents efuse write
>+ * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/wr=
ite
>+ *		1 - represents puf user fuse row number.
>+ *
>+ * this structure stores all the required details to
>+ * read/write efuse memory.
>+ */
>+struct xilinx_efuse {
>+	u64 src;
>+	u32 size;
>+	u32 offset;
>+	enum efuse_access flag;
>+	u32 pufuserfuse;
>+};
>+
>+static int zynqmp_efuse_access(void *context, unsigned int offset,
>+			       void *val, size_t bytes, enum efuse_access flag,
>+			       unsigned int pufflag)
>+{
>+	struct device *dev =3D context;
>+	struct xilinx_efuse *efuse;
>+	dma_addr_t dma_addr;
>+	dma_addr_t dma_buf;
>+	size_t words =3D bytes / WORD_INBYTES;
>+	int ret;
>+	int value;
>+	char *data;
>+
>+	if (bytes % WORD_INBYTES !=3D 0) {
>+		dev_err(dev, "Bytes requested should be word aligned\n");
>+		return -EOPNOTSUPP;
>+	}
>+
>+	if (pufflag =3D=3D 0 && offset % WORD_INBYTES) {
>+		dev_err(dev, "Offset requested should be word aligned\n");
>+		return -EOPNOTSUPP;
>+	}
>+
>+	if (pufflag =3D=3D 1 && flag =3D=3D EFUSE_WRITE) {
>+		memcpy(&value, val, bytes);
>+		if ((offset =3D=3D EFUSE_PUF_START_OFFSET ||
>+		     offset =3D=3D EFUSE_PUF_MID_OFFSET) &&
>+		    value & P_USER_0_64_UPPER_MASK) {
>+			dev_err(dev, "Only lower 4 bytes are allowed to be
>programmed in P_USER_0 & P_USER_64\n");
>+			return -EOPNOTSUPP;
>+		}
>+
>+		if (offset =3D=3D EFUSE_PUF_END_OFFSET &&
>+		    (value & P_USER_127_LOWER_4_BIT_MASK)) {
>+			dev_err(dev, "Only MSB 28 bits are allowed to be
>programmed for P_USER_127\n");
>+			return -EOPNOTSUPP;
>+		}
>+	}
>+
>+	efuse =3D dma_alloc_coherent(dev, sizeof(struct xilinx_efuse),
>+				   &dma_addr, GFP_KERNEL);
>+	if (!efuse)
>+		return -ENOMEM;
>
>-static int zynqmp_nvmem_read(void *context, unsigned int offset,
>-			     void *val, size_t bytes)
>+	data =3D dma_alloc_coherent(dev, sizeof(bytes),
>+				  &dma_buf, GFP_KERNEL);
>+	if (!data) {
>+		ret =3D -ENOMEM;
>+		goto efuse_data_fail;
>+	}
>+
>+	if (flag =3D=3D EFUSE_WRITE) {
>+		memcpy(data, val, bytes);
>+		efuse->flag =3D EFUSE_WRITE;
>+	} else {
>+		efuse->flag =3D EFUSE_READ;
>+	}
>+
>+	efuse->src =3D dma_buf;
>+	efuse->size =3D words;
>+	efuse->offset =3D offset;
>+	efuse->pufuserfuse =3D pufflag;
>+
>+	zynqmp_pm_efuse_access(dma_addr, (u32 *)&ret);
>+	if (ret !=3D 0) {
>+		if (ret =3D=3D EFUSE_NOT_ENABLED) {
>+			dev_err(dev, "efuse access is not enabled\n");
>+			ret =3D -EOPNOTSUPP;
>+		} else {
>+			dev_err(dev, "Error in efuse read %x\n", ret);
>+			ret =3D -EPERM;
>+		}
>+		goto efuse_access_err;
>+	}
>+
>+	if (flag =3D=3D EFUSE_READ)
>+		memcpy(val, data, bytes);
>+efuse_access_err:
>+	dma_free_coherent(dev, sizeof(bytes),
>+			  data, dma_buf);
>+efuse_data_fail:
>+	dma_free_coherent(dev, sizeof(struct xilinx_efuse),
>+			  efuse, dma_addr);
>+
>+	return ret;
>+}
>+
>+static int zynqmp_nvmem_read(void *context, unsigned int offset, void
>+*val, size_t bytes)
> {
> 	struct device *dev =3D context;
> 	int ret;
>+	int pufflag =3D 0;
> 	int idcode;
> 	int version;
>
>-	ret =3D zynqmp_pm_get_chipid(&idcode, &version);
>-	if (ret < 0)
>-		return ret;
>+	if (offset >=3D EFUSE_PUF_START_OFFSET && offset <=3D
>EFUSE_PUF_END_OFFSET)
>+		pufflag =3D 1;
>+
>+	switch (offset) {
>+	/* Soc version offset is zero */
>+	case SOC_VERSION_OFFSET:
>+		if (bytes !=3D SOC_VER_SIZE)
>+			return -EOPNOTSUPP;
>+
>+		ret =3D zynqmp_pm_get_chipid((u32 *)&idcode, (u32
>*)&version);
>+		if (ret < 0)
>+			return ret;
>+
>+		dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
>+		*(int *)val =3D version & SILICON_REVISION_MASK;
>+		break;
>+	/* Efuse offset starts from 0xc */
>+	case EFUSE_START_OFFSET ... EFUSE_END_OFFSET:
>+	case EFUSE_PUF_START_OFFSET ... EFUSE_PUF_END_OFFSET:
>+		ret =3D zynqmp_efuse_access(context, offset, val,
>+					  bytes, EFUSE_READ, pufflag);
>+		break;
>+	default:
>+		*(u32 *)val =3D 0xDEADBEEF;
>+		ret =3D 0;
>+		break;
>+	}
>+
>+	return ret;
>+}
>+
>+static int zynqmp_nvmem_write(void *context,
>+			      unsigned int offset, void *val, size_t bytes) {
>+	int pufflag =3D 0;
>+
>+	if (offset < EFUSE_START_OFFSET || offset > EFUSE_PUF_END_OFFSET)
>+		return -EOPNOTSUPP;
>
>-	dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
>-	*(int *)val =3D version & SILICON_REVISION_MASK;
>+	if (offset >=3D EFUSE_PUF_START_OFFSET && offset <=3D
>EFUSE_PUF_END_OFFSET)
>+		pufflag =3D 1;
>
>-	return 0;
>+	return zynqmp_efuse_access(context, offset,
>+				   val, bytes, EFUSE_WRITE, pufflag);
> }
>
> static const struct of_device_id zynqmp_nvmem_match[] =3D { @@ -45,11
>+211,11 @@ static int zynqmp_nvmem_probe(struct platform_device *pdev)
> 	econfig.name =3D "zynqmp-nvmem";
> 	econfig.owner =3D THIS_MODULE;
> 	econfig.word_size =3D 1;
>-	econfig.size =3D 1;
>+	econfig.size =3D ZYNQMP_NVMEM_SIZE;
> 	econfig.dev =3D dev;
> 	econfig.add_legacy_fixed_of_cells =3D true;
>-	econfig.read_only =3D true;
> 	econfig.reg_read =3D zynqmp_nvmem_read;
>+	econfig.reg_write =3D zynqmp_nvmem_write;
>
> 	return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig));  }
>--
>2.37.6

Acked-by: Kalyani Akula <Kalyani.akula@amd.com>
=20
Regards,
Kalyani