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Message-ID: <4eb13d801cd227e8682f10804025f5b6da2dfafc.camel@gmail.com>
Subject: Re: [PATCH 2/2] iio: adc: ad4130: only set GPIO_CTRL if pin is
 unused
From: Nuno =?ISO-8859-1?Q?S=E1?= <noname.nuno@gmail.com>
To: Cosmin Tanislav <demonsingur@gmail.com>
Cc: Cosmin Tanislav <cosmin.tanislav@analog.com>, Lars-Peter Clausen
	 <lars@metafoo.de>, Michael Hennerich <Michael.Hennerich@analog.com>, 
	Jonathan Cameron
	 <jic23@kernel.org>, Andy Shevchenko <andy.shevchenko@gmail.com>, 
	linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org
Date: Thu, 08 Feb 2024 09:16:39 +0100
In-Reply-To: <20240207132007.253768-2-demonsingur@gmail.com>
References: <20240207132007.253768-1-demonsingur@gmail.com>
	 <20240207132007.253768-2-demonsingur@gmail.com>
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On Wed, 2024-02-07 at 15:20 +0200, Cosmin Tanislav wrote:
> Currently, GPIO_CTRL bits are set even if the pins are used for
> measurements.
>=20
> GPIO_CTRL bits should only be set if the pin is not used for
> other functionality.
>=20
> Fix this by only setting the GPIO_CTRL bits if the pin has no
> other function.
>=20
> Fixes: 62094060cf3a ("iio: adc: ad4130: add AD4130 driver")
> Signed-off-by: Cosmin Tanislav <demonsingur@gmail.com>
> ---

Reviewed-by: Nuno Sa <nuno.sa@analog.com>

> =C2=A0drivers/iio/adc/ad4130.c | 10 +++++++---
> =C2=A01 file changed, 7 insertions(+), 3 deletions(-)
>=20
> diff --git a/drivers/iio/adc/ad4130.c b/drivers/iio/adc/ad4130.c
> index c7df499f9775..febb64e67955 100644
> --- a/drivers/iio/adc/ad4130.c
> +++ b/drivers/iio/adc/ad4130.c
> @@ -1864,10 +1864,14 @@ static int ad4130_setup(struct iio_dev *indio_dev=
)
> =C2=A0		return ret;
> =C2=A0
> =C2=A0	/*
> -	 * Configure all GPIOs for output. If configured, the interrupt
> function
> -	 * of P2 takes priority over the GPIO out function.
> +	 * Configure unused GPIOs for output. If configured, the interrupt
> +	 * function of P2 takes priority over the GPIO out function.
> =C2=A0	 */
> -	val =3D=C2=A0 AD4130_IO_CONTROL_GPIO_CTRL_MASK;
> +	val =3D 0;
> +	for (i =3D 0; i < AD4130_MAX_GPIOS; i++)
> +		if (st->pins_fn[i + AD4130_AIN2_P1] =3D=3D AD4130_PIN_FN_NONE)
> +			val |=3D FIELD_PREP(AD4130_IO_CONTROL_GPIO_CTRL_MASK,
> BIT(i));
> +
> =C2=A0	val |=3D FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st-
> >int_pin_sel);
> =C2=A0
> =C2=A0	ret =3D regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val);