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Message-ID: <63d59bff272f572c94f97000475c4ac3e157c013.camel@redhat.com>
Subject: Re: [PATCH v2] net: phy: dp83822: Fix RGMII TX delay configuration
From: Paolo Abeni <pabeni@redhat.com>
To: Tim Pambor <tp@osasysteme.de>, Andrew Lunn <andrew@lunn.ch>
Cc: Heiner Kallweit <hkallweit1@gmail.com>, Russell King
 <linux@armlinux.org.uk>,  "David S. Miller" <davem@davemloft.net>, Eric
 Dumazet <edumazet@google.com>, Jakub Kicinski <kuba@kernel.org>, Dan Murphy
 <dmurphy@ti.com>, netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Date: Thu, 08 Feb 2024 11:12:28 +0100
In-Reply-To: <20240204101128.49336-1-tp@osasysteme.de>
References: <20240204101128.49336-1-tp@osasysteme.de>
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On Sun, 2024-02-04 at 11:11 +0100, Tim Pambor wrote:
> The logic for enabling the TX clock shift is inverse of enabling the RX
> clock shift. The TX clock shift is disabled when DP83822_TX_CLK_SHIFT is
> set. Correct the current behavior and always write the delay configuratio=
n
> to ensure consistent delay settings regardless of bootloader configuratio=
n.
>=20
> Reference: https://www.ti.com/lit/ds/symlink/dp83822i.pdf p. 69
>=20
> Fixes: 8095295292b5 ("net: phy: DP83822: Add setting the fixed internal d=
elay")
> Signed-off-by: Tim Pambor <tp@osasysteme.de>
> ---
> Changes in v2:
>   - Further cleanup of RGMII configuration

This overall makes the change more invasive, I'm unsure is in the
direction pointed by Russell

>   - Check for errors setting DP83822_RGMII_MODE_EN
> ---
>  drivers/net/phy/dp83822.c | 41 +++++++++++++--------------------------
>  1 file changed, 14 insertions(+), 27 deletions(-)
>=20
> diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
> index b7cb71817780..1b2c34a97396 100644
> --- a/drivers/net/phy/dp83822.c
> +++ b/drivers/net/phy/dp83822.c
> @@ -380,42 +380,29 @@ static int dp83822_config_init(struct phy_device *p=
hydev)
>  {
>  	struct dp83822_private *dp83822 =3D phydev->priv;
>  	struct device *dev =3D &phydev->mdio.dev;
> -	int rgmii_delay;
> -	s32 rx_int_delay;
> -	s32 tx_int_delay;
> +	int rcsr_mask =3D DP83822_RGMII_MODE_EN;
> +	int rcsr =3D 0;
>  	int err =3D 0;
>  	int bmcr;
> =20
>  	if (phy_interface_is_rgmii(phydev)) {
> -		rx_int_delay =3D phy_get_internal_delay(phydev, dev, NULL, 0,
> -						      true);
> +		rcsr |=3D DP83822_RGMII_MODE_EN;
> =20
> -		if (rx_int_delay <=3D 0)
> -			rgmii_delay =3D 0;
> -		else
> -			rgmii_delay =3D DP83822_RX_CLK_SHIFT;
> +		/* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */
> +		if (phy_get_internal_delay(phydev, dev, NULL, 0, true) > 0)
> +			rcsr |=3D DP83822_RX_CLK_SHIFT;
> =20
> -		tx_int_delay =3D phy_get_internal_delay(phydev, dev, NULL, 0,
> -						      false);
> -		if (tx_int_delay <=3D 0)
> -			rgmii_delay &=3D ~DP83822_TX_CLK_SHIFT;
> -		else
> -			rgmii_delay |=3D DP83822_TX_CLK_SHIFT;
> +		/* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */
> +		if (phy_get_internal_delay(phydev, dev, NULL, 0, false) <=3D 0)
> +			rcsr |=3D DP83822_TX_CLK_SHIFT;
> =20
> -		if (rgmii_delay) {
> -			err =3D phy_set_bits_mmd(phydev, DP83822_DEVADDR,
> -					       MII_DP83822_RCSR, rgmii_delay);
> -			if (err)
> -				return err;
> -		}
> -
> -		phy_set_bits_mmd(phydev, DP83822_DEVADDR,
> -					MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
> -	} else {
> -		phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
> -					MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
> +		rcsr_mask |=3D DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT;

It looks like there is a change of behavior here. The current code
clear the DP83822_RGMII_MODE_EN, while this patch will clear
DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, leaving
DP83822_RGMII_MODE_EN unmodified.

It does not look correct to me.

Cheers,

Paolo