Received: by 2002:a05:7412:3b8b:b0:fc:a2b0:25d7 with SMTP id nd11csp205004rdb; Thu, 8 Feb 2024 03:45:36 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWDQVuqAeU/RwWR+6oe8OdZUAOg0IFOGSXQS9/lda232cyJ9+5AqO3q3nlwMR1F2Ju9NWPQsewE5N7w6iFKW+8OnSVsLrok/Y3eLzIctw== X-Google-Smtp-Source: AGHT+IFa+KVUP142RNmRIORRogqH186Par/D3Flk3FfUBo2RIZmiqRzbG/CgnVI1tMIbiVdqcfoy X-Received: by 2002:a05:6358:33a5:b0:175:67e3:f9be with SMTP id i37-20020a05635833a500b0017567e3f9bemr6172230rwd.31.1707392736492; Thu, 08 Feb 2024 03:45:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707392736; cv=pass; d=google.com; s=arc-20160816; b=ALAoc54XNS/PC23J/MHePvk/38uYwVHbxMTIeOlL2t+f+0xgKZzxLjmdrw7QMmiOxr otj64Et5kZ8eNKT61x4fJUwthJi71mHAohjYsjVT+byJCBTfeJ0HVZrRr7UunP9SjvTf yY94qDYCcdCZzmY3bMaZna6cUQ6Slxr5J3TmSG3k+Qu4A8pUspu6dXPC18/3EBSG4JbP DyJdhiIbEoivAJ98H9jJal9QiNrYOEx1BC4lR6Ifjr+/Pg1VwU6q2bzrdz2MgkYD2ilv kYB+57qDbhL45ddGcKwcxtyMhW5ecd53v31Atx7PD+ED5CNb7FL+0oDnbBEd8HLJ6GQZ T0TQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:message-id:content-transfer-encoding:mime-version :list-unsubscribe:list-subscribe:list-id:precedence:subject:date :from:dkim-signature; bh=+5FtVfQOYc9W4Tivrll/t7jheULdfNTnw9gRQlUXSec=; fh=SzwLNh4VkrCLuPU/4J2aGNGZVujCLq3wA9NafKqik0Y=; b=0XEIqAxLr401kDqMNbpthmEsMxEuEJjRkS24Lw/Un8MGlkfW6Bh9J9zVaf+3VdtCCG JXjVkAv0Y6YZLHf6sX5R5KU2XCPG1NHaNJZJYC0pOYssPcEp+FhryxhIpa0eRZNTvfrm V0jzzzgsVXSRu3CV2jAY4HlYh0y+bx7YiS31dgjs8i34u4CxANJjWN+2vigNDp9e7R6L FbkuOr1H8zC+J3yccp+Fy/RZZmThx4H7dq2zEH07LSuN08c9lrPwmgVKIuN8Y5o32YqU Q8pZZjl3Du4bQbnalcq1KlS9lN6MjiaWNz5GDIDC+DwU+oLdDqUBlyHy0R382rM/G9WC N25g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=RmnrDl+N; arc=pass (i=1 spf=pass spfdomain=microchip.com dkim=pass dkdomain=microchip.com dmarc=pass fromdomain=microchip.com); spf=pass (google.com: domain of linux-kernel+bounces-57984-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57984-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=microchip.com X-Forwarded-Encrypted: i=2; AJvYcCV3+q3iaZEln+jf9TE47za13Io4EAX2ilyCMOyJe+JwbzQxNuqPn4fybMUnx+CmXLxbOSo0rk5OjAvEdoYkXoXFhFNeyo+TN7V6u8U9SQ== Return-Path: Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id s68-20020a635e47000000b005bd27be66e1si3496007pgb.719.2024.02.08.03.45.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 03:45:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-57984-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=RmnrDl+N; arc=pass (i=1 spf=pass spfdomain=microchip.com dkim=pass dkdomain=microchip.com dmarc=pass fromdomain=microchip.com); spf=pass (google.com: domain of linux-kernel+bounces-57984-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57984-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=microchip.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 63D0728B041 for ; Thu, 8 Feb 2024 11:45:07 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6A5F06F07C; Thu, 8 Feb 2024 11:44:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="RmnrDl+N" Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1A386EB70; Thu, 8 Feb 2024 11:44:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707392698; cv=none; b=F9v2WfOkPCrlNTrxzgXrqpnNOqIRIj3HyWEHEf/mseb/FmLfMUW58svpcAVJIO6WEU3zLWqdTrPq8lgoEfemnQMhA5cZuBCJZ7B3BjLUygcefG7ElDp+Oa4p+/aTvFNBk4fJznXDnEaeRQ9SceaZu+Pgk0wL1zG3nbV5O0+07KI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707392698; c=relaxed/simple; bh=4RLrpLO9Lr9DKthkMv9dYVS7bKcH7m8SKjLUBGgExck=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:To:CC; b=ASgQq/bIsgpv7sDXYsZBvh4yYwX9ZMpQFEm2XcoJh0Ez8jjAEWBIwCYOJrHlKqXauQNiagNSKLCgkUBiWRfUYgGwThRGKcswV80/f6I1LpyyAE2ylMU2zNF7NQeMte5VUYsEPPNQUOmKxGwhuz23g76aezGv2Kge+D1FsQZbH1o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=RmnrDl+N; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1707392695; x=1738928695; h=from:date:subject:mime-version:content-transfer-encoding: message-id:to:cc; bh=4RLrpLO9Lr9DKthkMv9dYVS7bKcH7m8SKjLUBGgExck=; b=RmnrDl+N3xQJo69LYDdDZp96I3eMI5CMPAYOtEdqt1lvjX8G1xX42JWo YR1QbtVoEcZSLBCTf9ogl7yfDGSetakXSdmcYmdY27XFoMBamYVP0fBRP HcLc295vQv3k8isqxvN92DQYa1uTh7Ez+aEBpX4DJXcXbrxmVRm0gR9Bf g8XKeSK9CJI62k4rfA1tB4aCpcDnaPsM1nKmmYaxx1ZRrWHy01f2nJxSx kRn6dmKAUALxa+ugEvMjxGRfGuXcBkF+5LrPVOqX31uW517ZiZUAB4OgU za7xO7LgqEJDEVtxShZxqE7uDq6rPw8r200UcLMI4Bz4mspx/7ZWi44zD g==; X-CSE-ConnectionGUID: 1FvkdppZRHmt/Dzk9vusdQ== X-CSE-MsgGUID: OJNdQtm/SPKx55/Ftri+9A== X-IronPort-AV: E=Sophos;i="6.05,253,1701154800"; d="scan'208";a="15964774" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 08 Feb 2024 04:44:54 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 8 Feb 2024 04:44:34 -0700 Received: from [10.40.56.22] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Thu, 8 Feb 2024 04:44:29 -0700 From: Nayab Sayed Date: Thu, 8 Feb 2024 17:12:12 +0530 Subject: [PATCH] dt-bindings: mtd: update references from partition.txt to mtd.yaml Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-ID: <20240208-partition-txt-v1-1-4398af3b7bb2@microchip.com> X-B4-Tracking: v=1; b=H4sIABO+xGUC/x2MQQqAIBAAvxJ7TjATsb4SHUy32ouJSgji35OOA zNTIWEkTLAOFSK+lOjxHaZxAHsbfyEj1xkEF5ILrlkwMVPuFsslM6cQudWHVMsMvQkRTyr/b9t b+wD7YKiJXwAAAA== To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stefan Agner , Lucas Stach , Thierry Reding , Jonathan Hunter , Han Xu CC: , , , , Nayab Sayed X-Mailer: b4 0.12.4 Commit f902baa917b6 ("dt-bindings: mtd: Remove useless file about partitions") removed the file partition.txt. Hence, in this commit, the lines mentioning this file are updated to reference mtd.yaml, which now includes partition{,s}.yaml. Signed-off-by: Nayab Sayed --- Documentation/devicetree/bindings/mtd/davinci-nand.txt | 2 +- Documentation/devicetree/bindings/mtd/flctl-nand.txt | 2 +- Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt | 2 +- Documentation/devicetree/bindings/mtd/gpio-control-nand.txt | 2 +- Documentation/devicetree/bindings/mtd/gpmi-nand.yaml | 2 +- Documentation/devicetree/bindings/mtd/hisi504-nand.txt | 2 +- Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt | 2 +- Documentation/devicetree/bindings/mtd/orion-nand.txt | 2 +- Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/davinci-nand.txt b/Documentation/devicetree/bindings/mtd/davinci-nand.txt index edebeae1f5b3..eb8e2ff4dbd2 100644 --- a/Documentation/devicetree/bindings/mtd/davinci-nand.txt +++ b/Documentation/devicetree/bindings/mtd/davinci-nand.txt @@ -68,7 +68,7 @@ Deprecated properties: false. Nand device bindings may contain additional sub-nodes describing partitions of -the address space. See partition.txt for more detail. The NAND Flash timing +the address space. See mtd.yaml for more detail. The NAND Flash timing values must be programmed in the chip select’s node of AEMIF memory-controller (see Documentation/devicetree/bindings/memory-controllers/ davinci-aemif.txt). diff --git a/Documentation/devicetree/bindings/mtd/flctl-nand.txt b/Documentation/devicetree/bindings/mtd/flctl-nand.txt index 427f46dc60ad..51518399d737 100644 --- a/Documentation/devicetree/bindings/mtd/flctl-nand.txt +++ b/Documentation/devicetree/bindings/mtd/flctl-nand.txt @@ -15,7 +15,7 @@ The DMA fields are not used yet in the driver but are listed here for completing the bindings. The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. +address space. See mtd.yaml for more detail. Example: diff --git a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt index 25f07c1f9e44..530c017e014e 100644 --- a/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt +++ b/Documentation/devicetree/bindings/mtd/fsl-upm-nand.txt @@ -22,7 +22,7 @@ Deprecated properties: (R/B# pins not connected). Each flash chip described may optionally contain additional sub-nodes -describing partitions of the address space. See partition.txt for more +describing partitions of the address space. See mtd.yaml for more detail. Examples: diff --git a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt index 486a17d533d7..0edf55d47ea8 100644 --- a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt @@ -26,7 +26,7 @@ Optional properties: read to ensure that the GPIO accesses have completed. The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. +address space. See mtd.yaml for more detail. Examples: diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml b/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml index ba086c34626d..021c0da0b072 100644 --- a/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml @@ -12,7 +12,7 @@ maintainers: description: | The GPMI nand controller provides an interface to control the NAND flash chips. The device tree may optionally contain sub-nodes - describing partitions of the address space. See partition.txt for + describing partitions of the address space. See mtd.yaml for more detail. properties: diff --git a/Documentation/devicetree/bindings/mtd/hisi504-nand.txt b/Documentation/devicetree/bindings/mtd/hisi504-nand.txt index 8963983ae7cb..362203e7d50e 100644 --- a/Documentation/devicetree/bindings/mtd/hisi504-nand.txt +++ b/Documentation/devicetree/bindings/mtd/hisi504-nand.txt @@ -22,7 +22,7 @@ The following ECC strength and step size are currently supported: - nand-ecc-strength = <16>, nand-ecc-step-size = <1024> Flash chip may optionally contain additional sub-nodes describing partitions of -the address space. See partition.txt for more detail. +the address space. See mtd.yaml for more detail. Example: diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt index e737e5beb7bf..4a00ec2b2540 100644 --- a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt +++ b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt @@ -39,7 +39,7 @@ Optional children node properties: - wp-gpios: GPIO specifier for the write protect pin. Optional child node of NAND chip nodes: -Partitions: see partition.txt +Partitions: see mtd.yaml Example: nand-controller@70008000 { diff --git a/Documentation/devicetree/bindings/mtd/orion-nand.txt b/Documentation/devicetree/bindings/mtd/orion-nand.txt index 2d6ab660e603..b9997b1f13ac 100644 --- a/Documentation/devicetree/bindings/mtd/orion-nand.txt +++ b/Documentation/devicetree/bindings/mtd/orion-nand.txt @@ -13,7 +13,7 @@ Optional properties: registers in usecs The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. +address space. See mtd.yaml for more detail. Example: diff --git a/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt b/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt index 09815c40fc8a..635455350660 100644 --- a/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt +++ b/Documentation/devicetree/bindings/mtd/samsung-s3c2410.txt @@ -19,7 +19,7 @@ Optional child properties: Each child device node may optionally contain a 'partitions' sub-node, which further contains sub-nodes describing the flash partition mapping. -See partition.txt for more detail. +See mtd.yaml for more detail. Example: --- base-commit: 547ab8fc4cb04a1a6b34377dd8fad34cd2c8a8e3 change-id: 20240208-partition-txt-d6ee0c8b4693 Best regards, -- Nayab Sayed