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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 8 Feb 2024 17:19:29 +0200
Message-ID: <CAA8EJprRF0tVFZK9c=MT8bSRcBdRvcugBaeEzpX5-wfRyNgc3Q@mail.gmail.com>
Subject: Re: [PATCH] arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes
To: Krishna Chaitanya Chundru <quic_krichai@quicinc.com>
Cc: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, 
	Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, 
	linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, 
	quic_ramkri@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, 
	quic_parass@quicinc.com
Content-Type: text/plain; charset="UTF-8"

On Thu, 8 Feb 2024 at 16:58, Krishna Chaitanya Chundru
<quic_krichai@quicinc.com> wrote:
> On 2/8/2024 12:21 PM, Dmitry Baryshkov wrote:
> > On Thu, 8 Feb 2024 at 08:14, Krishna Chaitanya Chundru
> > <quic_krichai@quicinc.com> wrote:
> >>
> >>
> >>
> >> On 2/7/2024 5:17 PM, Dmitry Baryshkov wrote:
> >>> On Wed, 7 Feb 2024 at 12:42, Krishna chaitanya chundru
> >>> <quic_krichai@quicinc.com> wrote:
> >>>>
> >>>> Enable PCIe1 controller and its corresponding PHY nodes on
> >>>> qcs6490-rb3g2 platform.
> >>>>
> >>>> PCIe switch is connected to PCIe1, PCIe switch has multiple endpoints
> >>>> connected. For each endpoint a unique BDF will be assigned and should
> >>>> assign unique smmu id. So for each BDF add smmu id.
> >>>>
> >>>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
> >>>> ---
> >>>>    arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 42 ++++++++++++++++++++++++++++
> >>>>    1 file changed, 42 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> >>>> index 8bb7d13d85f6..0082a3399453 100644
> >>>> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> >>>> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
> >>>> @@ -413,6 +413,32 @@ vreg_bob_3p296: bob {
> >>>>           };
> >>>>    };
> >>>>
> >>>> +&pcie1 {
> >>>> +       perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> >>>> +
> >>>> +       pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
> >>>> +       pinctrl-names = "default";
> >>>> +
> >>>> +       iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
> >>>> +                   <0x100 &apps_smmu 0x1c81 0x1>,
> >>>> +                   <0x208 &apps_smmu 0x1c84 0x1>,
> >>>> +                   <0x210 &apps_smmu 0x1c85 0x1>,
> >>>> +                   <0x218 &apps_smmu 0x1c86 0x1>,
> >>>> +                   <0x300 &apps_smmu 0x1c87 0x1>,
> >>>> +                   <0x400 &apps_smmu 0x1c88 0x1>,
> >>>> +                   <0x500 &apps_smmu 0x1c89 0x1>,
> >>>> +                   <0x501 &apps_smmu 0x1c90 0x1>;
> >>>
> >>> Is the iommu-map really board specific?
> >>>
> >> The iommu-map for PCIe varies if PCIe switch is connected.
> >> For this platform a PCIe switch is connected and for that reason
> >> we need to define additional smmu ID's for each BDF.
> >>
> >> For that reason we defined here as these ID's are applicable only
> >> for this board.
> >
> > So, these IDs are the same for all boards, just being unused on
> > devices which have no bridges / switches connected to this PCIe host.
> > If this is correct, please move them to sc7280.dtsi.
> >
> Yes ID's will be same for all boards. we can move them sc7280.dtsi
> but the BDF to smmu mapping will be specific to this board only.
> if there is some other PCIe switch with different configuration is
> connected to different board of same variant in future again these
> mapping needs to updated.

Could you possibly clarify this? Are they assigned one at a time
manually? Or is it somehow handled by the board's TZ code, which
assigns them sequentially to the known endpoints? And is it done via
probing the link or via some static configuration?

>
> For that reason I tried to add it here.
>
> - Krishna Chaitanya.
> >>
> >> - Krishna Chaitanya.
> >>>> +
> >>>> +       status = "okay";
> >>>> +};
> >>>> +
> >>>> +&pcie1_phy {
> >>>> +       vdda-phy-supply = <&vreg_l10c_0p88>;
> >>>> +       vdda-pll-supply = <&vreg_l6b_1p2>;
> >>>> +
> >>>> +       status = "okay";
> >>>> +};
> >>>> +
> >>>>    &qupv3_id_0 {
> >>>>           status = "okay";
> >>>>    };
> >>>> @@ -420,6 +446,22 @@ &qupv3_id_0 {
> >>>>    &tlmm {
> >>>>           gpio-reserved-ranges = <32 2>, /* ADSP */
> >>>>                                  <48 4>; /* NFC */
> >>>> +
> >>>> +       pcie1_reset_n: pcie1-reset-n-state {
> >>>> +               pins = "gpio2";
> >>>> +               function = "gpio";
> >>>> +               drive-strength = <16>;
> >>>> +               output-low;
> >>>> +               bias-disable;
> >>>> +       };
> >>>> +
> >>>> +       pcie1_wake_n: pcie1-wake-n-state {
> >>>> +               pins = "gpio3";
> >>>> +               function = "gpio";
> >>>> +               drive-strength = <2>;
> >>>> +               bias-pull-up;
> >>>> +       };
> >>>> +
> >>>>    };
> >>>>
> >>>>    &uart5 {
> >>>>
> >>>> ---
> >>>> base-commit: 70d201a40823acba23899342d62bc2644051ad2e
> >>>> change-id: 20240207-enable_pcie-95b1d6612b27
> >>>>
> >>>> Best regards,
> >>>> --
> >>>> Krishna chaitanya chundru <quic_krichai@quicinc.com>
> >>>>
> >>>>
> >>>
> >>>
> >
> >
> >


-- 
With best wishes
Dmitry