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Message-ID: <49067f872e56d6f315a8b1b93bea92e54cba4874.camel@ndufresne.ca>
Subject: Re: [PATCH v2] dt-bindings: media: Add sram-size Property for Wave5
From: Nicolas Dufresne <nicolas@ndufresne.ca>
To: Nishanth Menon <nm@ti.com>, Krzysztof Kozlowski
	 <krzysztof.kozlowski@linaro.org>
Cc: Brandon Brnich <b-brnich@ti.com>, Nas Chung <nas.chung@chipsnmedia.com>,
  Jackson Lee <jackson.lee@chipsnmedia.com>, Mauro Carvalho Chehab
 <mchehab@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski
 <krzysztof.kozlowski+dt@linaro.org>,  Conor Dooley <conor+dt@kernel.org>,
 linux-media@vger.kernel.org, devicetree@vger.kernel.org, 
 linux-kernel@vger.kernel.org, Vignesh Raghavendra <vigneshr@ti.com>, Darren
 Etheridge <detheridge@ti.com>
Date: Fri, 09 Feb 2024 12:22:02 -0500
In-Reply-To: <20240202125257.p4astjuxpzr5ltjs@dragster>
References: <20240201184238.2542695-1-b-brnich@ti.com>
	 <1209b7cf-5be2-4107-aa6b-d67a32ea3737@linaro.org>
	 <20240202125257.p4astjuxpzr5ltjs@dragster>
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Le vendredi 02 f=C3=A9vrier 2024 =C3=A0 06:52 -0600, Nishanth Menon a =C3=
=A9crit=C2=A0:
> On 11:47-20240202, Krzysztof Kozlowski wrote:
> > On 01/02/2024 19:42, Brandon Brnich wrote:
> > > Wave521c has capability to use SRAM carveout to store reference data =
with
> > > purpose of reducing memory bandwidth. To properly use this pool, the =
driver
> > > expects to have an sram and sram-size node. Without sram-size node, d=
river
> > > will default value to zero, making sram node irrelevant.
> >=20
> > I am sorry, but what driver expects should not be rationale for new
> > property. This justification suggests clearly it is not a property for =
DT.
> >=20
>=20
> Yup, the argumentation in the commit message is from the wrong
> perspective. bindings are OS agnostic hardware description, and what
> driver does with the description is driver's problem.
>=20
> I will at least paraphrase my understanding:
> In this case, however, the hardware block will limp along with
> the usage of DDR (as is the current description), due to the
> latencies involved for DDR accesses. However, the hardware block
> has capability to use a substantially lower latency SRAM to provide
> proper performance and hence for example, deal with higher resolution

nit: I'd suggest to refer to "higher bandwidth" to generalize the combinati=
on
formed by resolution and frame rate. The resolution is always fixed with th=
is
IP, regardless if its fast enough of not. It may not match the stream creat=
or
intended frame rate though, which such optimization may fix.

> data streams. This SRAM is instantiated at SoC level rather than
> embedded within the hardware block itself.
>=20
>=20