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Date: Fri, 9 Feb 2024 17:25:57 +0000
From: Mark Brown <broonie@kernel.org>
To: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Dave Martin <Dave.Martin@arm.com>,
	Jackson Cooper-Driver <Jackson.Cooper-Driver@arm.com>,
	linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] arm64/sme: Restore SMCR on exit from suspend
Message-ID: <ZcZgJaZy+57ERBnm@finisterre.sirena.org.uk>
References: <20240203-arm64-sme-resume-v2-0-a1fbaddc4425@kernel.org>
 <20240203-arm64-sme-resume-v2-1-a1fbaddc4425@kernel.org>
 <20240209164648.GA24829@willie-the-truck>
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On Fri, Feb 09, 2024 at 04:46:48PM +0000, Will Deacon wrote:

> Looking at the other places where we touch SMCR_EL1, it looks like we
> always use a read-modify-write sequence. However, doesn't that mean we
> inherit a bunch of unknown bits on cold boot? I'm basically wondering
> whether we should be initialising these registers to a well-known value
> earlier in the CPU init path, a bit like we do for the EL2 variants.

That'd be safer from a future proofing point of view, yes - we've got a
similar pattern with ZCR as well from the looks of it.  I'll send a
separate series.

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