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Message-ID: <542e7f15-3898-4396-a8ff-7972d3308132@linux.microsoft.com>
Date: Fri, 9 Feb 2024 10:58:36 -0800
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Subject: Re: [RFC PATCH] KVM: arm64: Override Microsoft Azure Cobalt 100 MIDR
 value with ARM Neoverse N2
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To: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>,
 Marc Zyngier <maz@kernel.org>, Oliver Upton <oliver.upton@linux.dev>,
 James Morse <james.morse@arm.com>, Suzuki K Poulose
 <suzuki.poulose@arm.com>, Zenghui Yu <yuzenghui@huawei.com>,
 Andre Przywara <andre.przywara@arm.com>, Rob Herring <robh@kernel.org>,
 Fuad Tabba <tabba@google.com>, Joey Gouly <joey.gouly@arm.com>,
 Kristina Martsenko <kristina.martsenko@arm.com>,
 "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)"
 <linux-arm-kernel@lists.infradead.org>,
 open list <linux-kernel@vger.kernel.org>,
 "open list:KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)"
 <kvmarm@lists.linux.dev>
References: <20240206195819.1146693-1-eahariha@linux.microsoft.com>
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 <ZcYNn5LDmH1g2dDB@FVFF77S0Q05N.cambridge.arm.com>
From: Easwar Hariharan <eahariha@linux.microsoft.com>
In-Reply-To: <ZcYNn5LDmH1g2dDB@FVFF77S0Q05N.cambridge.arm.com>
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On 2/9/2024 3:33 AM, Mark Rutland wrote:
> On Thu, Feb 08, 2024 at 11:16:10AM -0800, Easwar Hariharan wrote:
>> On 2/7/2024 1:49 AM, Mark Rutland wrote:
>>> On Tue, Feb 06, 2024 at 07:58:16PM +0000, Easwar Hariharan wrote:
>>> Further, if Azure Cobalt 100 is based on ARM Neoverse N2, you presumably suffer
>>> from the same errata; can you comment on that at all? e.g. are there any
>>> changes in this part that *might* lead to differences in errata and/or
>>> workarounds? How do the MIDR_EL1.{Variant,Revision} values compare to that of
>>> Neoverse N2?
>>
>> Yes, Azure Cobalt 100 suffers from the same errata as Neoverse N2. We had changes
>> in the implementation, but according to our hardware folks, the Neoverse N2 errata
>> we are affected by so far aren't affected by the changes made for Azure Cobalt 100.
> 
> Ok, so of the currently-known-and-mitigated errata, you'll be affected by:
> 
> 	ARM64_ERRATUM_2139208
> 	ARM64_ERRATUM_2067961
> 	ARM64_ERRATUM_2253138
> 
> ... and we'll need to extend the midr_range lists for those errata to cover
> Azure Cobalt 100.
> 
>>From your patch, it looks like the Azure Cobalt 100 MIDR value (0x6D0FD490) is
> the same as the Arm Neoverse-N2 r0p0 MIDR value (0x410FD490), except the
> 'Implementer' field is 0x6D ('m' in ASCII) rather than 0x41 ('A' in ASCII).
> 
> Are you happy to send a patch extending arch/arm64/include/asm/cputype.h with
> the relevant ARM_CPU_IMP_* and CPU_PART_* definitions, and use those to extend
> the midr_range lists for those errata?

Yes.

> 
> As above, if you could make any comment on how the MIDR_EL1.{Variant,Revision}
> fields map to that of Arm Neoverse-N2, it would be very helpful. It's not clear
> to me whether those fields correspond directly (and so this part is based on
> r0p0), or whether you have a different scheme for revision numbers. That'll
> matter for correctly matching any future errata and/or future revisions of
> Azure Cobalt 100.
> 

Thanks for the clarifying detail on your question. Azure Cobalt 100 is indeed based
on r0p0 of the Neoverse N-2 and we have not used a different scheme than Neoverse N2
for the Variant and Revision fields.


> Mark.
> 
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