Received-SPF: pass (google.com: domain of linux-kernel+bounces-59930-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1;
Date: Fri, 9 Feb 2024 12:22:01 -0800
From: Dan Williams <dan.j.williams@intel.com>
To: Robert Richter <rrichter@amd.com>, Davidlohr Bueso <dave@stgolabs.net>,
	Jonathan Cameron <jonathan.cameron@huawei.com>, Dave Jiang
	<dave.jiang@intel.com>, Alison Schofield <alison.schofield@intel.com>, Vishal
 Verma <vishal.l.verma@intel.com>, Ira Weiny <ira.weiny@intel.com>, Dan
 Williams <dan.j.williams@intel.com>
CC: Robert Richter <rrichter@amd.com>, Jonathan Cameron
	<Jonathan.Cameron@huawei.com>, <linux-cxl@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: RE: [PATCH] cxl/pci: Fix disabling CXL memory for zero-based
 addressing
Message-ID: <65c68969903b1_afa429460@dwillia2-xfh.jf.intel.com.notmuch>
References: <20240209193451.163564-1-rrichter@amd.com>
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <20240209193451.163564-1-rrichter@amd.com>
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?mCFNDGBnrL0rGHXmKnxzknwZJZB9MpME5Szst9x3ePNYlkyvyBXh66/h8xUn?=
 =?us-ascii?Q?CpPEmzB9qDraMFx5F5HzDcvnSjLm+havGRQ/eDQCfFEl+NtrN+8JYuErezg5?=
 =?us-ascii?Q?eASCSXPtY2NYsKznX1Aa3p6LS2eNWEoEm9Tx72JRQWWvUzM0OG+hnj1i6mj0?=
 =?us-ascii?Q?l9VbkMkmpQSCkXkm0yd3lc602ClW+OCBipdkyx+4/6o06NOUYowxwecayu9C?=
 =?us-ascii?Q?9dpImRpInYLa4GgEy40tTo7Dn5KQe5f9YOtD1I+Bj5iY7crolcvZYhIq+OFo?=
 =?us-ascii?Q?KVL93S9hiD1MPfiA7boIdAnwKfGlS8B1cLPBwF4FxGwS1J7rpHp/VvzRnUOA?=
 =?us-ascii?Q?yWPXewzfuskfs9cOPb4kzYCCFFgaGmld327NUWNqA5PQ+AwJuvHn+gLxRub5?=
 =?us-ascii?Q?Swj8OMBiKQT/UufgO7smzi4tc+UtaZ9gq0XvYcgfHCTrSWkqkH4yNx13FY2I?=
 =?us-ascii?Q?3o0F7WqZFIEd62OcU5nv+BnFqJ19wYmKjU5b23vEAqsSMb5GPn2/DnH9VZib?=
 =?us-ascii?Q?0fpYUEOU9/gNx/zvxYqFaBYr+2AVO252GNinXZkjwR2bamjVga3i1gvE0vkW?=
 =?us-ascii?Q?RUzp7ofZZzx0Z+jdHAs3q+wTRMwKDOm7FaTUhaCrfCxuY0ALbkhDUy+HSZYy?=
 =?us-ascii?Q?0a3a69BXF+n5BNJBqZIVzAuvw385vbMvF/AqI7uecawUn7wkWzfdun6y5kDy?=
 =?us-ascii?Q?hp2LtV/+KZaLIqOr4RZFVPs9fMMJLUUpnun81ApSTySCczPqbmND8hAzY+Ce?=
 =?us-ascii?Q?3/zRM/4epfp+MgTYkN7JNXDU3cTPW+tCUxwxq2/E9ySsgQVhIk0BsmG3q9yZ?=
 =?us-ascii?Q?ei6Hg9+S/4e0GU1M3hp9pN4o6rcYRAGNxG+WWiDEx+KNUCh0hFCODByr58z9?=
 =?us-ascii?Q?ng6Cs5KJh38jF37fMPOQ5zdcBzJqpxVQWDUneRVVa2X436x05EP1ZDXrIAbK?=
 =?us-ascii?Q?hXSEEHu8jt6mTEScZC5GeFTrfLUSNIeGCA2tRCuADZadGWOCx8v0a8yDutxH?=
 =?us-ascii?Q?3LFvP2C8wmNwZBxEotxhDp2HZhrKtmIHFwttmoPRaPwbKqYKeGQ1X6Xe7f3X?=
 =?us-ascii?Q?xuzQlzNK+CIUYXJijeQtmfm/Oc2FfCS6+Lkx/c+SKVbMdC9SO8MiwkT+PzY9?=
 =?us-ascii?Q?DtjGitQ17gTSj+NZef7OD8+D/yTk257gBL69WFpT9v2b7qaAVz/KobUdYpAt?=
 =?us-ascii?Q?mtopD+ca9wBpKwBrXfEdsePrmdsGea/HfMl3Mec9ls/uSjXFsrnIZpH0Ez4z?=
 =?us-ascii?Q?U0KT6RjVSde42bbmVT9DXx7mXyLih/JhhrJfXDrIy8dAs9AETroqVxGwSKa0?=
 =?us-ascii?Q?/T0cj7XnHm/JzaGYxzJE5XwTbzbC74To0o5POTffqree7/SILMtQ5izFEiMn?=
 =?us-ascii?Q?xRrmkG+ycEJURmN5kze3pbjFv9R8dOnGBv3TvoVWEZrJIvElHMOPoy/XZfta?=
 =?us-ascii?Q?ScL+Ef05paRrmorqa3eXiqs2AhzMV/OPIxYt6h5m3UiDNPcsIeE7MyvKraVi?=
 =?us-ascii?Q?uHRIQlTvJzeSd7kvtVt++S7ZqF+psnQQvxaezmKKFoJRgrcddOUJRvshgpRf?=
 =?us-ascii?Q?4ajInFSVLfMw1Ojfn3n4Isdz2CfOgW932uc58jZQGRWf3Ufta6VE6JH0iiD9?=
 =?us-ascii?Q?/Q=3D=3D?=
X-MS-Exchange-CrossTenant-Network-Message-Id: 06270a1e-3162-4c6f-916a-08dc29acc780
X-MS-Exchange-CrossTenant-AuthSource: PH8PR11MB8107.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Feb 2024 20:22:03.9095
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: s+3f+7acq8hD/6pKE812SMu2v1ynxgZ1Px3iFNeo7ECeU23QQJBy8i/6DsFswmyWWKNCDQdS08mo3qVVr61+LPdclI85woyC1AwOIPYDE50=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB5600
X-OriginatorOrg: intel.com

Robert Richter wrote:
> Based on CPU implementation and architecture, the CXL memory address
> decode per memory channel can be implemented as zero based address for
> addressing the CXL attached memory. In such case, the CXL host
> physical address may not match the system address. The CFMWS contains
> CXL ranges that are based on the system address range for the host
> physical address and may not match with the CXL decoders.
> 
> During HDM decoder setup, the DVSEC CXL range registers (cxl-3.1,
> 8.1.3.8) are checked if the memory is enabled and the CXL range is in
> an HPA window that is described in a CFMWS structure of the CXL host
> bridge (cxl-3.1, 9.18.1.3).
> 
> Now, if the range registers are programmed with zero-based addresses,
> the ranges do not match the CFMWS windows and the CXL memory range
> will be disabled. The HDM decoder stops working then which causes
> system memory being disabled and further a kernel hang during HDM
> decoder initialization, typically when a CXL enabled kernel boots.
> 
> If the decoder is programmed with a zero-based hardware address and
> the range is enabled, the CXL memory range is then in use by the
> system.
> 
> Fix a kernel hang due to disabling of CXL memory during HDM decoder
> initialization by adding a check for zero-based address ranges, mark
> such ranges as used which prevents the CXL memory from being disabled.
> 
> Note this patch only fixes HDM initialization for zero-based address
> ranges and a kernel hang this may cause. Decoder setup still does not
> enable the HPA ranges for zero-based address ranges, the HDM decoder
> cannot be added then and the kernel shows a message like the
> following:
> 
>  cxl decoder1.0: failed to add to region: 0x0-0x3ffffffff
> 
> However, support for this can be added in a later series.
> 
> Fix for stable, please add stable tag.
> 
> Fixes: 9de321e93c3b ("cxl/pci: Refactor cxl_hdm_decode_init()")
> Fixes: 34e37b4c432c ("cxl/port: Enable HDM Capability after validating DVSEC Ranges")
> Signed-off-by: Robert Richter <rrichter@amd.com>
> ---
>  drivers/cxl/core/pci.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 569354a5536f..3a36a2f0c94f 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -466,6 +466,18 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
>  	for (i = 0, allowed = 0; info->mem_enabled && i < info->ranges; i++) {
>  		struct device *cxld_dev;
>  
> +		/*
> +		 * Handle zero-based hardware addresses
> +		 */
> +		if (!info->dvsec_range[i].start &&
> +		    info->dvsec_range[i].end != CXL_RESOURCE_NONE &&
> +		    info->dvsec_range[i].end) {
> +			dev_dbg(dev, "Zero-based hardware range found [%#llx - %#llx]\n",
> +				info->dvsec_range[i].start, info->dvsec_range[i].end);
> +			allowed++;
> +			continue;
> +		}
> +

I am not comfortable with this. It should be checking a platform
specific quirk, or similar for the possibility of HPA != SPA. The
entirety of the Linux CXL subsystem is built on the assumption that HPA
== SPA, and if a platform wants to inject an offset between those Linux
needs some way to enumerate that it is running in that new world. Yes,
nothing in the CXL specification precludes HPA != SPA, but Linux has
long since shipped the opposite assumption.