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Sun, 11 Feb 2024 15:15:15 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCVadT3SJadJYIB5Auk8+YrOhtUifoFH0HG9icPCnV8HbUCiA2Qb+3xxDXIwmI3Ng1c3oU1E9G2Ny3dIeZKk7rVScGnaHOEF24jcmRqg5G2WSeE9dhfr3rNxSuXiBELIvUS3Iz+B1aOIN/A2qqelaGBo0P1tnzz0m6CqQqGEaodhuyA+IFjFSRoV6aHqGnl3P468Jh+kVm6POWcYKDbNvpjr1nJS8SST7bNcfa9jgqBEBmeLlLMCPETO23OafWgjY58sIjblMBLoblqRKpaSxiYlMCnig9jXO6+NBAzDD0RciSfWEr+h2YVr6EuY6T8CIjZ26wK0uoUVTpfeDcjLpNc9rrabbO4ZEDKk6oeI6cqsml8zicqFjpvf4zFMQhbsSJr9Zazr0dfaW4N7sNRnEozSpaW/vDH7AtGh75nxYjd9Rq0zz+dIcTgxdus= Received: from aford-System-Version.lan ([2601:447:d002:5be:c8c4:8542:9142:2184]) by smtp.gmail.com with ESMTPSA id e9-20020ac81309000000b0042c7b74e767sm280955qtj.22.2024.02.11.15.15.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Feb 2024 15:15:15 -0800 (PST) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Cc: marex@denx.de, aford@beaconembedded.com, Adam Ford , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: imx8mn: Slow default video_pll clock rate Date: Sun, 11 Feb 2024 17:15:08 -0600 Message-ID: <20240211231508.188567-1-aford173@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Since commit 8208181fe536 ("clk: imx: composite-8m: Add imx8m_divider_determine_rate") the lcdif controller has had the ability to set the disp_pixel_clk rate which propagates up the tree and sets the video_pll rate automatically. By setting this value low, it will force the recalculation of video_pll to the lowest rate needed by lcdif instead of dividing a larger clock down to the desired clock speed. This has the advantage of being able to lower the video_pll rate from 594MHz to 148.5MHz when operating at 1080p. It can go even lower when operating at lower resolutions and refresh rates. Signed-off-by: Adam Ford diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 136e75c51251..932c8b05c75f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1168,7 +1168,7 @@ disp_blk_ctrl: blk-ctrl@32e28000 { <&clk IMX8MN_SYS_PLL1_800M>; assigned-clock-rates = <266000000>, <24000000>, - <594000000>, + <24000000>, <500000000>, <200000000>; #power-domain-cells = <1>; -- 2.43.0