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Date: Mon, 12 Feb 2024 07:59:36 +0000
From: Conor Dooley <conor.dooley@microchip.com>
To: Samuel Holland <samuel.holland@sifive.com>
CC: Andrew Jones <ajones@ventanamicro.com>, Palmer Dabbelt
	<palmer@dabbelt.com>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <stable@kernel.org>
Subject: Re: [PATCH -fixes 2/2] riscv: Save/restore envcfg CSR during CPU
 suspend
Message-ID: <20240212-sneezing-lifter-d7d390f764e1@wendy>
References: <20240212022642.1968739-1-samuel.holland@sifive.com>
 <20240212022642.1968739-2-samuel.holland@sifive.com>
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On Sun, Feb 11, 2024 at 06:26:15PM -0800, Samuel Holland wrote:
> The value of the [ms]envcfg CSR is lost when entering a nonretentive
> idle state, so the CSR must be rewritten when resuming the CPU.
>=20
> Because the [ms]envcfg CSR is part of the base RISC-V privileged ISA
> specification, it cannot be detected from the ISA string. However, most
> existing hardware is too old to implement this CSR. As a result, it must
> be probed at runtime.
>=20
> Extend the logic for the Zicsr ISA extension to probe for the presence
> of specific CSRs. Since the CSR number is encoded as an immediate value
> within the csrr instruction, a switch case is necessary for any CSR that
> must be probed this way. Use the exception table to handle the illegal
> instruction exception raised when the CSR is not implemented.
>=20
> Cc: stable@kernel.org
> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode")
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>

On nommu:

  /build/tmp.RcQwFfgWA4/arch/riscv/kernel/cpufeature.c:967:21: error: expec=
ted ':' or ')' before '_ASM_EXTABLE'
  /build/tmp.RcQwFfgWA4/arch/riscv/kernel/cpufeature.c:967:34: error: inval=
id suffix "b" on integer constant
  /build/tmp.RcQwFfgWA4/arch/riscv/kernel/cpufeature.c:967:38: error: inval=
id suffix "b" on integer constant

https://patchwork.kernel.org/project/linux-riscv/patch/20240212022642.19687=
39-2-samuel.holland@sifive.com/

Cheers,
Conor.

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