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Message-ID: <58cdf104-acda-6215-cbaa-188c304da9f3@quicinc.com>
Date: Mon, 12 Feb 2024 15:17:19 +0530
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Subject: Re: [RFC 7/7] arm64: dts: qcom: x1e80100: Enable LLCC/DDR dvfs
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To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
CC: <sudeep.holla@arm.com>, <cristian.marussi@arm.com>, <andersson@kernel.org>,
        <konrad.dybcio@linaro.org>, <jassisinghbrar@gmail.com>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <quic_rgottimu@quicinc.com>,
        <quic_kshivnan@quicinc.com>, <conor+dt@kernel.org>
References: <20240117173458.2312669-1-quic_sibis@quicinc.com>
 <20240117173458.2312669-8-quic_sibis@quicinc.com>
 <CAA8EJpo5F==whKMVFgPAM+=DpB+=KzPhKt-poGXuHxy-KSxe8Q@mail.gmail.com>
From: Sibi Sankar <quic_sibis@quicinc.com>
In-Reply-To: <CAA8EJpo5F==whKMVFgPAM+=DpB+=KzPhKt-poGXuHxy-KSxe8Q@mail.gmail.com>
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On 1/18/24 02:17, Dmitry Baryshkov wrote:
> On Wed, 17 Jan 2024 at 19:37, Sibi Sankar <quic_sibis@quicinc.com> wrote:
>>
>> Enable LLCC/DDR dvfs through the Qualcomm's SCMI vendor protocol.
> 
> Could you please post DT bindings?

ack, will include it in the next re-spin.

> 
>>
>> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 48 ++++++++++++++++++++++++++
>>   1 file changed, 48 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index 6856a206f7fc..3dc6f32fbb4c 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -329,6 +329,54 @@ scmi_dvfs: protocol@13 {
>>                                  reg = <0x13>;
>>                                  #clock-cells = <1>;
>>                          };
>> +
>> +                       scmi_vendor: protocol@80 {
>> +                               reg = <0x80>;
>> +
>> +                               memlat {
> 
> This doesn't look like a generic node name.
> 
>> +                                       #address-cells = <1>;
>> +                                       #size-cells = <0>;
> 
>> +
>> +                                       memory@0 {
>> +                                               reg = <0x0>; /* Memory Type DDR */
>> +                                               freq-table-khz = <200000 4224000>;
>> +
>> +                                               monitor-0 {
>> +                                                       qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>;
> 
> 
> 
>> +                                                       qcom,cpufreq-memfreq-tbl = < 999000 547000 >,
>> +                                                                                  < 1440000 768000 >,
>> +                                                                                  < 1671000 1555000 >,
>> +                                                                                  < 2189000 2092000 >,
>> +                                                                                  < 2156000 3187000 >,
>> +                                                                                  < 3860000 4224000 >;
> 
> These tables should be rewritten as OPP tables. >
> 
>> +                                               };
>> +
>> +                                               monitor-1 {
>> +                                                       qcom,compute-mon;
>> +                                                       qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>;
>> +                                                       qcom,cpufreq-memfreq-tbl = < 1440000 200000 >,
>> +                                                                                  < 2189000 768000 >,
>> +                                                                                  < 2156000 1555000 >,
>> +                                                                                  < 3860000 2092000 >;
>> +                                               };
>> +                                       };
>> +
>> +                                       memory@1 {
>> +                                               reg = <0x1>; /* Memory Type LLCC */
>> +                                               freq-table-khz = <300000 1067000>;
>> +
>> +                                               monitor-0 {
>> +                                                       qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>;
>> +                                                       qcom,cpufreq-memfreq-tbl = < 999000 300000 >,
>> +                                                                                  < 1440000 466000 >,
>> +                                                                                  < 1671000 600000 >,
>> +                                                                                  < 2189000 806000 >,
>> +                                                                                  < 2156000 933000 >,
>> +                                                                                  < 3860000 1066000 >;
>> +                                               };
>> +                                       };
>> +                               };
>> +                       };
>>                  };
>>          };
>>
>> --
>> 2.34.1
>>
>>
> 
> 
> --
> With best wishes
> Dmitry