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Mon, 12 Feb 2024 02:50:39 -0800 (PST) X-Received: by 2002:a17:906:3507:b0:a3c:2293:6500 with SMTP id r7-20020a170906350700b00a3c22936500mr3694493eja.62.1707735039576; Mon, 12 Feb 2024 02:50:39 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20231230172351.574091-1-michael.roth@amd.com> <20231230172351.574091-31-michael.roth@amd.com> In-Reply-To: <20231230172351.574091-31-michael.roth@amd.com> From: Paolo Bonzini Date: Mon, 12 Feb 2024 11:50:26 +0100 Message-ID: Subject: Re: [PATCH v11 30/35] KVM: x86: Add gmem hook for determining max NPT mapping level To: Michael Roth Cc: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, mingo@redhat.com, jroedel@suse.de, thomas.lendacky@amd.com, hpa@zytor.com, ardb@kernel.org, seanjc@google.com, vkuznets@redhat.com, jmattson@google.com, luto@kernel.org, dave.hansen@linux.intel.com, slp@redhat.com, pgonda@google.com, peterz@infradead.org, srinivas.pandruvada@linux.intel.com, rientjes@google.com, dovmurik@linux.ibm.com, tobin@ibm.com, bp@alien8.de, vbabka@suse.cz, kirill@shutemov.name, ak@linux.intel.com, tony.luck@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, alpergun@google.com, jarkko@kernel.org, ashish.kalra@amd.com, nikunj.dadhania@amd.com, pankaj.gupta@amd.com, liam.merwick@oracle.com, zhi.a.wang@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sat, Dec 30, 2023 at 6:32=E2=80=AFPM Michael Roth = wrote: > int max_order, r; > + u8 max_level; > > if (!kvm_slot_can_be_private(fault->slot)) { > kvm_mmu_prepare_memory_fault_exit(vcpu, fault); > @@ -4321,8 +4322,15 @@ static int kvm_faultin_pfn_private(struct kvm_vcpu= *vcpu, > return r; > } > > - fault->max_level =3D min(kvm_max_level_for_order(max_order), > - fault->max_level); > + max_level =3D kvm_max_level_for_order(max_order); > + r =3D static_call(kvm_x86_gmem_max_level)(vcpu->kvm, fault->pfn, > + fault->gfn, &max_level); Might as well pass &fault->max_level directly to the callback, with no change to the vendor-specific code. I'll include the MMU part in a generic series to be the base for both Intel TDX and AMD SEV-SNP, and will do that change. Paolo > + if (r) { > + kvm_release_pfn_clean(fault->pfn); > + return r; > + } > + > + fault->max_level =3D min(max_level, fault->max_level); > fault->map_writable =3D !(fault->slot->flags & KVM_MEM_READONLY); > > return RET_PF_CONTINUE; > diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c > index 85f63b6842b6..5eb836b73131 100644 > --- a/arch/x86/kvm/svm/sev.c > +++ b/arch/x86/kvm/svm/sev.c > @@ -4315,3 +4315,30 @@ void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_= t end) > pfn +=3D use_2m_update ? PTRS_PER_PMD : 1; > } > } > + > +int sev_gmem_max_level(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, u8 *ma= x_level) > +{ > + int level, rc; > + bool assigned; > + > + if (!sev_snp_guest(kvm)) > + return 0; > + > + rc =3D snp_lookup_rmpentry(pfn, &assigned, &level); > + if (rc) { > + pr_err_ratelimited("SEV: RMP entry not found: GFN %llx PF= N %llx level %d error %d\n", > + gfn, pfn, level, rc); > + return -ENOENT; > + } > + > + if (!assigned) { > + pr_err_ratelimited("SEV: RMP entry is not assigned: GFN %= llx PFN %llx level %d\n", > + gfn, pfn, level); > + return -EINVAL; > + } > + > + if (level < *max_level) > + *max_level =3D level; > + > + return 0; > +} > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c > index f26b8c2a8be4..f745022f7454 100644 > --- a/arch/x86/kvm/svm/svm.c > +++ b/arch/x86/kvm/svm/svm.c > @@ -5067,6 +5067,7 @@ static struct kvm_x86_ops svm_x86_ops __initdata = =3D { > .alloc_apic_backing_page =3D svm_alloc_apic_backing_page, > > .gmem_prepare =3D sev_gmem_prepare, > + .gmem_max_level =3D sev_gmem_max_level, > .gmem_invalidate =3D sev_gmem_invalidate, > }; > > -- > 2.25.1 >