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Message-ID: <994c6ff1-96ed-4dde-94a1-43f6cab2a005@ti.com>
Date: Mon, 12 Feb 2024 17:33:54 +0530
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Subject: Re: [PATCH 1/4] arm64: dts: ti: k3-am62p: Fix memory ranges for DMSS
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To: Jai Luthra <j-luthra@ti.com>, Nishanth Menon <nm@ti.com>,
        Vignesh
 Raghavendra <vigneshr@ti.com>,
        Tero Kristo <kristo@kernel.org>, Rob Herring
	<robh+dt@kernel.org>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>, Andrew Davis <afd@ti.com>,
        Bryan Brattlof <bb@ti.com>, Dhruva Gole
	<d-gole@ti.com>
CC: <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, Devarsh Thakkar <devarsht@ti.com>,
        Aradhya
 Bhatia <a-bhatia1@ti.com>
References: <20240201-am62p_csi-v1-0-c83bb9eaeb49@ti.com>
 <20240201-am62p_csi-v1-1-c83bb9eaeb49@ti.com>
From: Vaishnav Achath <vaishnav.a@ti.com>
In-Reply-To: <20240201-am62p_csi-v1-1-c83bb9eaeb49@ti.com>
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Hi Jai,

Thanks for the patch.

On 01/02/24 18:37, Jai Luthra wrote:
> The INTR module for DMASS1 (CSI specific DMASS) is outside the currently
> available ranges, as it starts at 0x4e400000. So fix the ranges property
> to enable programming the interrupts correctly.
> 
> Fixes: 29075cc09f43 ("arm64: dts: ti: Introduce AM62P5 family of SoCs")
> Signed-off-by: Jai Luthra <j-luthra@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-am62p.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
> index 84ffe7b9dcaf..4f22b5d9fb9f 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi
> @@ -71,7 +71,7 @@ cbass_main: bus@f0000 {
>   			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
>   			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
>   			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
> -			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
> +			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */

Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com>

>   			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
>   			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
>   			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
>