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Mon, 12 Feb 2024 12:28:38 GMT Received: from [10.204.67.124] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 12 Feb 2024 04:28:32 -0800 Message-ID: <7932ccbb-3b41-49e2-bb88-9c2633002a0d@quicinc.com> Date: Mon, 12 Feb 2024 17:58:29 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: qcm6490-idp: add display and panel Content-Language: en-US To: Konrad Dybcio , Dmitry Baryshkov CC: , , , , , , , , , , , , , , , , , , References: <20240116094935.9988-1-quic_riteshk@quicinc.com> <20240116094935.9988-3-quic_riteshk@quicinc.com> <20a8efd1-e243-434e-8f75-aa786ac8014f@linaro.org> <99a9a562-9f6f-411c-be1c-0a28fc2524dd@quicinc.com> <9d1c684f-51ac-4d9c-a189-940ff65e0cab@linaro.org> From: Ritesh Kumar In-Reply-To: <9d1c684f-51ac-4d9c-a189-940ff65e0cab@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ERe9fjQUvxdTw12Qkc_kIo02E4PHDDAu X-Proofpoint-ORIG-GUID: ERe9fjQUvxdTw12Qkc_kIo02E4PHDDAu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-12_09,2024-02-12_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 adultscore=0 bulkscore=0 impostorscore=0 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1011 mlxscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402120092 On 1/23/2024 11:34 PM, Konrad Dybcio wrote: > > > On 1/23/24 16:12, Dmitry Baryshkov wrote: >> On Tue, 23 Jan 2024 at 15:43, Ritesh Kumar >> wrote: >>> >>> >>> On 1/16/2024 6:27 PM, Dmitry Baryshkov wrote: >>> >>>> On Tue, 16 Jan 2024 at 14:06, Konrad Dybcio >>>> wrote: >>>>> >>>>> >>>>> On 1/16/24 10:49, Ritesh Kumar wrote: >>>>>> Enable Display Subsystem with Novatek NT36672E Panel >>>>>> on qcm6490 idp platform. >>>>>> >>>>>> Signed-off-by: Ritesh Kumar >>>>>> --- >>>>>>     arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 100 >>>>>> +++++++++++++++++++++++ >>>>>>     1 file changed, 100 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>>>>> b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>>>>> index 2a6e4907c5ee..efa5252130a1 100644 >>>>>> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>>>>> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >>>>>> @@ -9,6 +9,7 @@ >>>>>>     #define PM7250B_SID 8 >>>>>>     #define PM7250B_SID1 9 >>>>>> >>>>>> +#include >>>>>>     #include >>>>>>     #include "sc7280.dtsi" >>>>>>     #include "pm7250b.dtsi" >>>>>> @@ -38,6 +39,25 @@ >>>>>>                 stdout-path = "serial0:115200n8"; >>>>>>         }; >>>>>> >>>>>> +     lcd_disp_bias: lcd-disp-bias-regulator { >>>>>> +             compatible = "regulator-fixed"; >>>>>> +             regulator-name = "lcd_disp_bias"; >>>>>> +             regulator-min-microvolt = <5500000>; >>>>>> +             regulator-max-microvolt = <5500000>; >>>>>> +             gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; >>>>>> +             enable-active-high; >>>>>> +             pinctrl-names = "default"; >>>>>> +             pinctrl-0 = <&lcd_disp_bias_en>; >>>>> property-n >>>>> property-names >>>>> >>>>> all throughout the patch >>> >>> Thanks, I will update in the new version. >>> >>>>>> +&gpu { >>>>>> +     status = "disabled"; >>>>>> +}; >>>>> Hm.. generally we disable the GPU in the SoC DT, but that doesn't >>>>> seem to have happened here.. >>>>> >>>>> Thinking about it more, is disabling it here necessary? Does it >>>>> not fail gracefully? >>>> Missed this. >>>> >>>> I'd say, I don't see a reason to disable it at all. The GPU should be >>>> working on sc7280 / qcm4290. >>> >>> With GPU device node enabled, adreno_bind failure is seen as the >>> "speed_bin" was not populated on QCM6490 target which leads to display >>> bind failure. >> >> Excuse me please. The GPU node for sc7280 already has speed_bin, which >> points to qfprom + 0x1e9, bits 5 to 9. >> >> Do you mean that qcm6490 uses different speed bin location? Or >> different values for the speed bins? >> >>> Spoke with GPU team and on QCM6490 board, only CPU rendering is >>> supported for now and there is no plan to enable GPU rendering in near >>> future. >> >> This sounds like having the feature disabled for no particular reason. >> Both the kernel and Mesa have supported the Adreno 635 for quite a >> while. > > 643 [1], [2] > >> >>> In this regard, what do you suggest >>> >>> 1) Disable GPU in QCM6490 DT (as per the current patch) >>> 2) Disable GPU in the SoC DT, but enable it in other platform DTs. >>> (This >>> will prompt change in all the dt's and we don't have all the devices to >>> test) >> >> The second option definitely follows what is present on other platforms. >> >>> Please let me know your views on it. >> >> Please enable the GPU instead. > > +1 > > Konrad > > [1] > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25408/diffs?commit_id=b1e851d66c3a3e53f1a464023f675f3f6cbd3503 > [2] > https://patches.linaro.org/project/linux-arm-msm/cover/20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org/ Thanks for the help. After applying missing patches from series https://patches.linaro.org/project/linux-arm-msm/cover/20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org/ in my local build, GPU is working fine. GPU disablement change is not needed. I will send new version of patch removing GPU part and addressing other review comments. Thanks, Ritesh