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AJvYcCUgmwaQShOWShi1suTDXaqKaPfmbpZ0oQAa37HQyxnAU97I6sNq454KZLHbsKYUGn/EwbDE29VAVK2LYcvBupDIC8vMG7eDMSTP6foO X-Gm-Message-State: AOJu0YyU0dC/D1Io9GXq+5R5zgzIxQa2dPERB+tweczZcBlu0WJpDyhk OnYnxE9j6Ga764IancjeCTEvZmfDxwsJVyqn2G5Td83BEpxUTqs8ku0VgUCKuZDBFKEq0QZU8kq X7PGqrvbz9mvpnWqzbLwr4VXI4aj3KOj+NzBauA== X-Received: by 2002:a25:b212:0:b0:dc7:46ab:9f5e with SMTP id i18-20020a25b212000000b00dc746ab9f5emr5777858ybj.29.1707743998897; Mon, 12 Feb 2024 05:19:58 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240212125239.7764-1-quic_vdadhani@quicinc.com> In-Reply-To: <20240212125239.7764-1-quic_vdadhani@quicinc.com> From: Dmitry Baryshkov Date: Mon, 12 Feb 2024 15:19:48 +0200 Message-ID: Subject: Re: [PATCH v4] i2c: i2c-qcom-geni: Correct I2C TRE sequence To: Viken Dadhaniya Cc: andersson@kernel.org, konrad.dybcio@linaro.org, andi.shyti@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, quic_bjorande@quicinc.com, manivannan.sadhasivam@linaro.org, bryan.odonoghue@linaro.org, quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com Content-Type: text/plain; charset="UTF-8" On Mon, 12 Feb 2024 at 14:52, Viken Dadhaniya wrote: > > For i2c read operation in GSI mode, we are getting timeout > due to malformed TRE basically incorrect TRE sequence > in gpi(drivers/dma/qcom/gpi.c) driver. > > I2C driver has geni_i2c_gpi(I2C_WRITE) function which generates GO TRE and > geni_i2c_gpi(I2C_READ)generates DMA TRE. Hence to generate GO TRE before > DMA TRE, we should move geni_i2c_gpi(I2C_WRITE) before > geni_i2c_gpi(I2C_READ) inside the I2C GSI mode transfer function > i.e. geni_i2c_gpi_xfer(). > > TRE stands for Transfer Ring Element - which is basically an element with > size of 4 words. It contains all information like slave address, > clk divider, dma address value data size etc). > > Mainly we have 3 TREs(Config, GO and DMA tre). > - CONFIG TRE : consists of internal register configuration which is > required before start of the transfer. > - DMA TRE : contains DDR/Memory address, called as DMA descriptor. > - GO TRE : contains Transfer directions, slave ID, Delay flags, Length > of the transfer. > > I2c driver calls GPI driver API to config each TRE depending on the > protocol. > > For read operation tre sequence will be as below which is not aligned > to hardware programming guide. > > - CONFIG tre > - DMA tre > - GO tre > > As per Qualcomm's internal Hardware Programming Guide, we should configure > TREs in below sequence for any RX only transfer. > > - CONFIG tre > - GO tre > - DMA tre > > Fixes: d8703554f4de ("i2c: qcom-geni: Add support for GPI DMA") > Reviewed-by: Andi Shyti > Reviewed-by: Bryan O'Donoghue > Tested-by: Bryan O'Donoghue # qrb5165-rb5 > Co-developed-by: Mukesh Kumar Savaliya > Signed-off-by: Mukesh Kumar Savaliya > Signed-off-by: Viken Dadhaniya Thank you, Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry