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From: Paolo Bonzini <pbonzini@redhat.com>
Date: Mon, 12 Feb 2024 18:01:54 +0100
Message-ID: <CABgObfYP4n12HOSx5XsibA==hmPCVe9hHZFTsJTTxBHA5pffwA@mail.gmail.com>
Subject: Re: [PATCH v18 040/121] KVM: x86/mmu: Disallow fast page fault on
 private GPA
To: isaku.yamahata@intel.com
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, 
	isaku.yamahata@gmail.com, erdemaktas@google.com, 
	Sean Christopherson <seanjc@google.com>, Sagi Shahar <sagis@google.com>, Kai Huang <kai.huang@intel.com>, 
	chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com
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On Tue, Jan 23, 2024 at 12:55=E2=80=AFAM <isaku.yamahata@intel.com> wrote:
>
> From: Isaku Yamahata <isaku.yamahata@intel.com>
>
> TDX requires TDX SEAMCALL to operate Secure EPT instead of direct memory
> access and TDX SEAMCALL is heavy operation.  Fast page fault on private G=
PA
> doesn't make sense.  Disallow fast page fault on private GPA.
>
> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  arch/x86/kvm/mmu/mmu.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
> index b2924bd9b668..54d4c8f1ba68 100644
> --- a/arch/x86/kvm/mmu/mmu.c
> +++ b/arch/x86/kvm/mmu/mmu.c
> @@ -3339,8 +3339,16 @@ static int kvm_handle_noslot_fault(struct kvm_vcpu=
 *vcpu,
>         return RET_PF_CONTINUE;
>  }
>
> -static bool page_fault_can_be_fast(struct kvm_page_fault *fault)
> +static bool page_fault_can_be_fast(struct kvm *kvm, struct kvm_page_faul=
t *fault)
>  {
> +       /*
> +        * TDX private mapping doesn't support fast page fault because th=
e EPT
> +        * entry is read/written with TDX SEAMCALLs instead of direct mem=
ory
> +        * access.
> +        */
> +       if (kvm_is_private_gpa(kvm, fault->addr))
> +               return false;

I think this does not apply to SNP? If so, it would be better to check
the SPTE against the shared-page mask inside the do...while loop.

Paolo

>         /*
>          * Page faults with reserved bits set, i.e. faults on MMIO SPTEs,=
 only
>          * reach the common page fault handler if the SPTE has an invalid=
 MMIO
> @@ -3450,7 +3458,7 @@ static int fast_page_fault(struct kvm_vcpu *vcpu, s=
truct kvm_page_fault *fault)
>         u64 *sptep;
>         uint retry_count =3D 0;
>
> -       if (!page_fault_can_be_fast(fault))
> +       if (!page_fault_can_be_fast(vcpu->kvm, fault))
>                 return ret;
>
>         walk_shadow_page_lockless_begin(vcpu);
> --
> 2.25.1
>