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Message-ID: <3a203d8b-861f-49bd-a196-c86e2d46123a@ti.com>
Date: Mon, 12 Feb 2024 11:56:23 -0600
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Subject: Re: [PATCH v2 0/7] Add tuning algorithm for delay chain
To: Francesco Dolcini <francesco@dolcini.it>
CC: Ulf Hansson <ulf.hansson@linaro.org>,
        Adrian Hunter
	<adrian.hunter@intel.com>, <linux-mmc@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
References: <20240207011520.3128382-1-jm@ti.com>
 <20240211160232.GB4443@francesco-nb>
 <7482f19f-b340-482f-bdf6-a5a68aeaf09e@ti.com>
 <20240212173244.GA17182@francesco-nb>
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From: Judith Mendez <jm@ti.com>
In-Reply-To: <20240212173244.GA17182@francesco-nb>
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Hi Francesco,

On 2/12/24 11:32 AM, Francesco Dolcini wrote:
> Hi Judith,
> 
> On Mon, Feb 12, 2024 at 10:33:35AM -0600, Judith Mendez wrote:
>> Hi Francesco,
>>
>> On 2/11/24 10:02 AM, Francesco Dolcini wrote:
>>> On Tue, Feb 06, 2024 at 07:15:13PM -0600, Judith Mendez wrote:
>>>> This patch series introduces a new tuning algorithm for
>>>> mmc. The new algorithm should be used when delay chain is
>>>> enabled. The ITAPDLY is selected from the largest passing
>>>> window and the buffer is not viewed as a circular buffer.
>>>> The new tuning algorithm is implemented as per the paper
>>>> published here [0] and has been tested on the following
>>>
>>> Where is this `[0]`?
>>
>> I must have missed linking the ref doc here, will add in next
>> iteration, thanks.
>>
>>>
>>>> platforms: AM62x SK, AM62A SK, AM62p SK, AM64x SK, and AM64x
>>>> EVM.
>>>
>>> In the other patches you link some document, but I was not able to find
>>> anything related to AM62, can you provide some reference on this
>>> specific SOC?
>>
>> This patch series fixes issues that affect all Sitara SoCs, not only
>> AM62x. However, I could use AM62x for reference, no problem.
> 
> I am really looking for documentation here that is related to the AM62
> because I was not able to find anything and this is a topic of interest
> for me.
> 

The AM62x device datasheet: https://www.ti.com/lit/ds/symlink/am625.pdf,
reference Table 7-79 for MMC0 and Table 7-97 for MMC1.

TRM, reference section 12.4.5 for MMCSD and section 12.4.5.5.2.3.2
Tuning Sequence that we currently implement in the sdhci_am654 driver.
Section 14.8.4.6 for MMCSD registers, SS_CFG_PHY_CTRL_1,
SS_CFG_PHY_CTRL_5, and SS_CFG_PHY_CTRL_5 are usually of higher interest.

Tuning algorithm, reference: 
https://www.ti.com/lit/an/spract9/spract9.pdf which is applicable for 
AM62x, DLL is not applicable
for AM62x, so the tuning algorithm should not consider the buffer
as a circular buffer.

~ Judith

> Can you share something?
> 
> Francesco
>