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Date: Mon, 12 Feb 2024 20:37:53 +0000
From: Conor Dooley <conor@kernel.org>
To: Miguel Ojeda <miguel.ojeda.sandonis@gmail.com>
Cc: Ramon de C Valle <rcvalle@google.com>, Trevor Gross <tmgross@umich.edu>,
	Conor Dooley <conor.dooley@microchip.com>,
	linux-riscv@lists.infradead.org, Miguel Ojeda <ojeda@kernel.org>,
	Alex Gaynor <alex.gaynor@gmail.com>,
	Wedson Almeida Filho <wedsonaf@gmail.com>,
	Boqun Feng <boqun.feng@gmail.com>, Gary Guo <gary@garyguo.net>,
	=?iso-8859-1?Q?Bj=F6rn?= Roy Baron <bjorn3_gh@protonmail.com>,
	Jonathan Corbet <corbet@lwn.net>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Nathan Chancellor <nathan@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	Tom Rix <trix@redhat.com>, rust-for-linux@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	llvm@lists.linux.dev, Matthew Maurer <mmaurer@google.com>,
	Sami Tolvanen <samitolvanen@google.com>
Subject: Re: [PATCH v1 0/2] RISC-V: enable rust
Message-ID: <20240212-outdoors-french-a40d57e38c71@spud>
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On Mon, Feb 12, 2024 at 08:17:31PM +0000, Conor Dooley wrote:
> On Mon, Feb 12, 2024 at 08:11:21PM +0100, Miguel Ojeda wrote:
> > On Mon, Feb 12, 2024 at 8:02=E2=80=AFPM Ramon de C Valle <rcvalle@googl=
e.com> wrote:
> > >
> > > Sorry for the late reply. Sami might be the best person to answer thi=
s, but KCFI (not CFI) tests are lowered by passes that are architecture spe=
cific (see https://reviews.llvm.org/D119296), so we'd need to add support f=
or RISC-V. There is no additional work required in the Rust compiler beside=
s enabling it for the new target.
> >=20
> > Thanks a lot Ramon!
> >=20
> > Then for RISC-V let's go for the `depends on` for the moment, and we
> > can remove when the support lands for RISC-V (ideally when someone has
> > managed to boot it at least under some configuration).
>=20
> If all you want is a boot under some configuration, that's not
> difficult. After all, I found the original issue by booting a kernel
> with CFI_CLANG enabled on the C side...

Also, regardless of depends on on RISC-V, things will still be broken
on arm64 and x86_64, since KCFI is not enabled in rustc there either?

> > There is no additional work required in the Rust compiler besides enabl=
ing it for the new target.
>=20
> This is not super clear though, it says "in the Rust compiler", not "in
> the kernel's buildsystem".

I realise I was not clear either. What I meant was that this talks about
rustc and not kbuild, so what is meant by "the new target" is not clear.
Do arm64 and x86_64 have functional support, so adding RISC-V in rustc
is needed, or did you mean for the new target in the kernel?


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