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Message-ID: <ca69d83d-90e9-4401-bac2-1782cd4e2318@sifive.com>
Date: Mon, 12 Feb 2024 21:25:20 -0600
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Subject: Re: [PATCH -fixes 2/2] riscv: Save/restore envcfg CSR during CPU
 suspend
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To: Stefan O'Rear <sorear@fastmail.com>,
 Andrew Jones <ajones@ventanamicro.com>, Palmer Dabbelt <palmer@dabbelt.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
 stable@kernel.org
References: <20240212022642.1968739-1-samuel.holland@sifive.com>
 <20240212022642.1968739-2-samuel.holland@sifive.com>
 <f1d370c1-a7d8-4240-a15a-a55616f5b4a6@app.fastmail.com>
From: Samuel Holland <samuel.holland@sifive.com>
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Hi Stefan,

On 2024-02-12 7:21 AM, Stefan O'Rear wrote:
> On Sun, Feb 11, 2024, at 9:26 PM, Samuel Holland wrote:
>> The value of the [ms]envcfg CSR is lost when entering a nonretentive
>> idle state, so the CSR must be rewritten when resuming the CPU.
>>
>> Because the [ms]envcfg CSR is part of the base RISC-V privileged ISA
>> specification, it cannot be detected from the ISA string. However, most
>> existing hardware is too old to implement this CSR. As a result, it must
>> be probed at runtime.
>>
>> Extend the logic for the Zicsr ISA extension to probe for the presence
>> of specific CSRs. Since the CSR number is encoded as an immediate value
>> within the csrr instruction, a switch case is necessary for any CSR that
>> must be probed this way. Use the exception table to handle the illegal
>> instruction exception raised when the CSR is not implemented.
> 
> We support non-conforming extensions, so we can't assume that if an
> implementation does not provide the Ss1p12 extension which defines senvcfg,
> the corresponding CSR number will not be used for other purposes.

Yes, you're right, I'll do this for v2. Though this does prevent us from
supporting hardware which implements senvcfg but not all of the rest of Ss1p12
(e.g. Ss1p11 + Zicboz).

Regards,
Samuel