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Message-ID: <619dd947-a3da-49ee-9bee-8b21c7e7ca1a@ti.com>
Date: Tue, 13 Feb 2024 11:43:17 +0530
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CC: <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
        <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,
        <vigneshr@ti.com>, <afd@ti.com>, <srk@ti.com>, <s-vadapalli@ti.com>
Subject: Re: [PATCH v3] dt-bindings: PCI: ti,j721e-pci-host: Add support for
 J722S SoC
To: <bhelgaas@google.com>, <lpieralisi@kernel.org>, <kw@linux.com>,
        <robh@kernel.org>, Conor Dooley <conor@kernel.org>
References: <20240124122936.816142-1-s-vadapalli@ti.com>
 <20240124-unmatched-plating-019a3055cf5e@spud>
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From: Siddharth Vadapalli <s-vadapalli@ti.com>
In-Reply-To: <20240124-unmatched-plating-019a3055cf5e@spud>
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On 24/01/24 21:40, Conor Dooley wrote:
> On Wed, Jan 24, 2024 at 05:59:36PM +0530, Siddharth Vadapalli wrote:
>> TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller.
>> The controller on J722S SoC is similar to the one present on TI's AM64
>> SoC, with the difference being that the controller on AM64 SoC supports
>> up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed.
>>
>> Update the bindings with a new compatible for J722S SoC.
>>
>> Technical Reference Manual of J722S SoC: https://www.ti.com/lit/zip/sprujb3
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

Bjorn, Rob,

Could you please merge this patch? This patch applies cleanly on the latest
linux-next tagged next-20240213.

> 
> Cheers,
> Conor.
> 
>> ---
>>
>> Hello,
>>
>> This patch is based on linux-next tagged next-20240124.
>>
>> v2:
>> https://lore.kernel.org/r/20240122064457.664542-1-s-vadapalli@ti.com/
>> Changes since v2:
>> - Added fallback compatible for "ti,j722s-pcie-host" as
>>   "ti,j721e-pcie-host" based on Conor's suggestion at:
>>   https://lore.kernel.org/r/20240122-getting-drippy-bb22a0634092@spud/#t
>>
>> v1:
>> https://lore.kernel.org/r/20240117102526.557006-1-s-vadapalli@ti.com/
>> Changes since v1:
>> - Dropped patches 1/3 and 2/3 of the v1 series as discussed in the v1
>>   thread.
>> - Updated patch 3/3 which is the v1 for this patch by dropping the checks
>>   for the "num-lanes" property and "max-link-speed" property since the PCI
>>   driver already validates the "num-lanes" property.
>>
>> Regards,
>> Siddharth.
>>
>>  Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
>> index b7a534cef24d..ac69deeaf1ee 100644
>> --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
>> +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
>> @@ -23,6 +23,10 @@ properties:
>>          items:
>>            - const: ti,j7200-pcie-host
>>            - const: ti,j721e-pcie-host
>> +      - description: PCIe controller in J722S
>> +        items:
>> +          - const: ti,j722s-pcie-host
>> +          - const: ti,j721e-pcie-host
>>  
>>    reg:
>>      maxItems: 4
>> -- 
>> 2.34.1
>>

-- 
Regards,
Siddharth.