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[209.85.219.176]) by smtp.gmail.com with ESMTPSA id a8-20020a256608000000b00dc6f1cdd45csm1557949ybc.22.2024.02.13.01.05.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 13 Feb 2024 01:05:47 -0800 (PST) Received: by mail-yb1-f176.google.com with SMTP id 3f1490d57ef6-dcbd1d4904dso1172226276.3; Tue, 13 Feb 2024 01:05:47 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCWlu7YEPScc5bUPIszVbUd0DICWdLwAW6Fu8qqhYrKycyerrJrM1lb3zgIKbl/ERtyTkfGuSkn0jRESIGxzG8pRCFAYF+juzyB8Efpifl9gx7YKOdHMMghzD8V4h+p5GGibiJyPbLoJJQiOQlvX9U7OYr9P4taN9rSJVcxurTC1Ou6M1bKD1OA+bCVy X-Received: by 2002:a25:bfcd:0:b0:dc6:c617:7ca with SMTP id q13-20020a25bfcd000000b00dc6c61707camr7330323ybm.29.1707815147208; Tue, 13 Feb 2024 01:05:47 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240213085912.56600-1-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20240213085912.56600-1-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 13 Feb 2024 10:05:35 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts To: Prabhakar Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das , Claudiu Beznea , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Feb 13, 2024 at 9:59=E2=80=AFAM Prabhakar wrote: > From: Lad Prabhakar > > All the RZ/G2L and alike SoC's (listed below) have ECCRAM0/1 interrupts > supported by the IRQC block, reflect the same in DT binding doc. > > - R9A07G043U - RZ/G2UL > - R9A07G044L/R9A07G044LC - RZ/{G2L,G2LC} > - R9A07G054 - RZ/V2L > - R9A08G045 - RZ/G3S > > For the RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts combined into singl= e > interrupt so we just use the below to represent them: > - ec7tie1-0 > - ec7tie2-0 > - ec7tiovf-0 > > Previously, it was assumed that BUS-error and ECCRAM0/1 error interrupts > were only supported by RZ/G2UL ("R9A07G043U") and RZ/G3S ("R9A08G045") > SoCs. However, in reality, all RZ/G2L and similar SoCs (listed above) > support these interrupts. Therefore, mark the 'interrupt-names' property > as required for all the SoCs and update the example node in the binding > document. > > Fixes: 96fed779d3d4 ("dt-bindings: interrupt-controller: Add Renesas RZ/G= 2L Interrupt Controller") > Fixes: 1cf0697a24ef ("dt-bindings: interrupt-controller: renesas,rzg2l-ir= qc: Document RZ/G3S") > Signed-off-by: Lad Prabhakar > --- > v2 -> v3: > - Fixed IRQ description as pointed by Geert > - Sending this individual patch as DTSI patches have been Reviewed by Gee= rt Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds