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Date: Tue, 13 Feb 2024 11:36:42 +0100 Message-Id: <20240213-xilinx_ecc-v8-0-8d75f8b80771@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIADpGy2UC/23MQQrCMBCF4auUWRuZJMZWV95Dithk2g5IWpIaI qV3N3bt8n/wvhUiBaYI12qFQIkjT75Ec6jAjk8/kGBXGhSqEyqpReYX+/wga0WjJfbGmDNKhHK YA/Wcd+zelh45LlP47HaSv/Uvk6RAQVpp7C5Yu66+zeSH9xImz/noCNpt277ak10qqQAAAA== To: Appana Durga Kedareswara rao , Naga Sureshkumar Relli , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Simek Cc: linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Srinivas Goud , Conor Dooley X-Mailer: b4 0.13-dev-f0463 X-Developer-Signature: v=1; a=openpgp-sha256; l=1791; i=mkl@pengutronix.de; h=from:subject:message-id; bh=NQFk6wv6h9t3jdfRJgwcW/SYE2bxvuDeigGOTR/4ws0=; b=owEBbQGS/pANAwAKASg4oj56LbxvAcsmYgBly0Y9E5T3iPK50/89vKqgjcywzg9volRy+nQIf dUYqANooaqJATMEAAEKAB0WIQRQQLqG4LYE3Sm8Pl8oOKI+ei28bwUCZctGPQAKCRAoOKI+ei28 b0E8CACYXyqGOOSlVUU8TCQhBIQYUM7pvlFJyeiYZH6lEk+WOOJlHzCRj7m2H7me41Ph+IsapmR Dhw0+wnW2N/gY38OdzFsVPiYm9D5LW8TeIV4KsMyx6k6+rekLJ4lvfgYYEbMKxZqtmliJAwwTOC JK82YS/oatenIiKRfMehabQrk6nNkxUn3Ax/ABdTPDE21DVZjy+AwWV1Fh5H6yarXmrdUXd0sDo Fq25I0WAhK8FICjoXMGwUEcyZWrjooJUFD8WLEJ8NNryH4uG1s0OTqlgYqrZ4TTJZwPVwqhS0Jk 97l52iA8Y4ynL8GY3JsxnNVFDZ6Wk5YwAFrysPByB8JKbn1D X-Developer-Key: i=mkl@pengutronix.de; a=openpgp; fpr=C1400BA0B3989E6FBC7D5B5C2B5EE211C58AEA54 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mkl@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org ECC is an IP configuration option where counter registers are added in IP for 1bit/2bit ECC errors count and reset. Also driver reports 1bit/2bit ECC errors for FIFOs based on ECC error interrupts. Add xlnx,has-ecc optional property for Xilinx AXI CAN controller to support ECC if the ECC block is enabled in the HW. Add ethtool stats interface for getting all the ECC errors information. There is no public documentation for it available. Changes in v8: - Use u64_stats_sync instead of spinlock - Renamed stats strings: use "_" instead of "-" - Renamed stats strings: add "_errors" trailer - Renamed stats variables similar to stats strings Changes in v7: - Update with spinlock only for stats counters Changes in v6: - Update commit description Changes in v5: - Fix review comments - Change the sequence of updates the stats - Add get_strings and get_sset_count stats interface - Use u64 stats helper function Changes in v4: - Fix DT binding check warning - Update xlnx,has-ecc property description Changes in v3: - Update mailing list - Update commit description Changes in v2: - Address review comments - Add ethtool stats interface - Update commit description --- Srinivas Goud (3): dt-bindings: can: xilinx_can: Add 'xlnx,has-ecc' optional property can: xilinx_can: Add ECC support can: xilinx_can: Add ethtool stats interface for ECC errors .../devicetree/bindings/net/can/xilinx,can.yaml | 5 + drivers/net/can/xilinx_can.c | 169 ++++++++++++++++++++- 2 files changed, 170 insertions(+), 4 deletions(-) --- base-commit: a3522a2edb3faf8cb98d38c2a99f5967beef24e2 change-id: 20240213-xilinx_ecc-8310f5556010 Best regards, -- Marc Kleine-Budde