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Tue, 13 Feb 2024 11:57:59 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 8704622AFEA; Tue, 13 Feb 2024 11:57:13 +0100 (CET) Received: from [10.201.22.200] (10.201.22.200) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 13 Feb 2024 11:57:12 +0100 Message-ID: Date: Tue, 13 Feb 2024 11:56:53 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 01/12] dt-bindings: memory-controller: st,stm32: add MP25 support To: Conor Dooley CC: , , , , , , , , , , References: <20240212174822.77734-1-christophe.kerello@foss.st.com> <20240212174822.77734-2-christophe.kerello@foss.st.com> <20240212-dial-strangle-0b6861b35ec9@spud> Content-Language: en-US From: Christophe Kerello In-Reply-To: <20240212-dial-strangle-0b6861b35ec9@spud> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-13_05,2024-02-12_03,2023-05-22_02 On 2/12/24 19:30, Conor Dooley wrote: > On Mon, Feb 12, 2024 at 06:48:11PM +0100, Christophe Kerello wrote: >> Add a new compatible string to support MP25 SOC. > > You're missing an explanation here as to why this mp25 is not compatible > with the mp1. > > Cheers, > Conor. > Hi Conor, On MP1 SoC, RNB signal (NAND controller signal) and NWAIT signal (PSRAM controler signal) have been integrated together in the SoC. That means that the NAND controller and the PSRAM controller (if the signal is used) can not be used at the same time. On MP25 SoC, the 2 signals can be used outside the SoC, so there is no more restrictions. MP1 SoC also embeds revision 1.1 of the FMC2 IP when MP25 SoC embeds revision 2.0 of the FMC2 IP. I will add this explanation in the commit message. Regards, Christophe Kerello. >> >> Signed-off-by: Christophe Kerello >> --- >> .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml >> index 14f1833d37c9..12e6afeceffd 100644 >> --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml >> +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml >> @@ -23,7 +23,9 @@ maintainers: >> >> properties: >> compatible: >> - const: st,stm32mp1-fmc2-ebi >> + enum: >> + - st,stm32mp1-fmc2-ebi >> + - st,stm32mp25-fmc2-ebi >> >> reg: >> maxItems: 1 >> -- >> 2.25.1 >>