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From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
In-Reply-To: <20240213142856.2416073-1-ericchancf@google.com>
References: <20240213142632.2415127-1-ericchancf@google.com> <20240213142856.2416073-1-ericchancf@google.com>
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Date: Tue, 13 Feb 2024 07:50:58 -0800
Message-ID: <CAJM55Z9qiQ6GpzKbYORQP12sz4V67UBGfWChZJeHvD_5j_d93Q@mail.gmail.com>
Subject: Re: [PATCH v3 1/4] riscv/barrier: Define __{mb,rmb,wmb}
To: Eric Chan <ericchancf@google.com>, paul.walmsley@sifive.com, palmer@dabbelt.com, 
	aou@eecs.berkeley.edu
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
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Eric Chan wrote:
> Introduce __{mb,rmb,wmb}, and rely on the generic definitions
> for {mb,rmb,wmb}.
> Although KCSAN is not yet support,
> it can be made more consistent with generic instrumentation.

nit: this commit message has some weird line breaks

>
> Signed-off-by: Eric Chan <ericchancf@google.com>
> ---
>  arch/riscv/include/asm/barrier.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
> index 110752594228..4c49a8ff2c68 100644
> --- a/arch/riscv/include/asm/barrier.h
> +++ b/arch/riscv/include/asm/barrier.h
> @@ -20,9 +20,9 @@
>  	__asm__ __volatile__ ("fence " #p "," #s : : : "memory")
>
>  /* These barriers need to enforce ordering on both devices or memory. */
> -#define mb()		RISCV_FENCE(iorw,iorw)
> -#define rmb()		RISCV_FENCE(ir,ir)
> -#define wmb()		RISCV_FENCE(ow,ow)
> +#define __mb()		RISCV_FENCE(iorw,iorw)
> +#define __rmb()		RISCV_FENCE(ir,ir)
> +#define __wmb()		RISCV_FENCE(ow,ow)
>
>  /* These barriers do not need to enforce ordering on devices, just memory. */
>  #define __smp_mb()	RISCV_FENCE(rw,rw)
> --
> 2.43.0.687.g38aa6559b0-goog
>
>
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