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bh=9ygk6/cDOkwUw/NJeAB8ipuDaGxiTdarNFVMbQnymP4=; b=WCZQ96no7Uxr4vdg3LIITz5RIEOfPQjFSy5qaYeILAtY/s6vghd9XGGREiwj1+EowB +K3kvEm2kB6ltir94lUUasBbF6Wx2avtna6r5Uph3Ku4D2Kgn9v5B2TbSxQyEivEsjA9 ay4hA0sXES1p6rxXFKsj4pGfPpdcayhlEqddZfoGm5OEjxZXVdqKko8thORmdlF7tD7X 9gRr2cnOhRvsnqrZWqX3iSjQoj/WtnOSf6B7Ej0JFZR1lvOAm5iqqWzScn5UsjYEyuZ1 pZy4m29ZoFZ13QmVDKJpU3jo+xCMZXZOS7v/jr+926gwU71pTt2pamQCV9NE3vQOb3oS LeGw== X-Gm-Message-State: AOJu0YwyhZD7vr7N6EY56vDrngW7a9yuSJeLRt7DswAFKCCOS1LlOD7B b1VFSakPIa7fuKDrOtpX9jjEMFJgjlSQ0mwKkYVAleQIpUZyD3CwOImj8MSefd0LHK7aAEufIV3 1kTtwhxkm+8RZ+hjAc4Bo1UOd1kH1ShsIhKCCzg== X-Received: by 2002:a2e:8755:0:b0:2d0:a6ef:651d with SMTP id q21-20020a2e8755000000b002d0a6ef651dmr6311505ljj.47.1707838089550; Tue, 13 Feb 2024 07:28:09 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240212-mainline-spi-precook-message-v1-0-a2373cd72d36@baylibre.com> <20240212-mainline-spi-precook-message-v1-5-a2373cd72d36@baylibre.com> In-Reply-To: From: David Lechner Date: Tue, 13 Feb 2024 09:27:58 -0600 Message-ID: Subject: Re: [PATCH 5/5] iio: adc: ad7380: use spi_optimize_message() To: =?UTF-8?B?TnVubyBTw6E=?= Cc: Mark Brown , Martin Sperl , David Jander , Jonathan Cameron , Michael Hennerich , =?UTF-8?B?TnVubyBTw6E=?= , Alain Volmat , Maxime Coquelin , Alexandre Torgue , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-iio@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Feb 13, 2024 at 3:47=E2=80=AFAM Nuno S=C3=A1 wrote: > > On Mon, 2024-02-12 at 17:26 -0600, David Lechner wrote: > > This modifies the ad7380 ADC driver to use spi_optimize_message() to > > optimize the SPI message for the buffered read operation. Since buffere= d > > reads reuse the same SPI message for each read, this can improve > > performance by reducing the overhead of setting up some parts the SPI > > message in each spi_sync() call. > > > > Signed-off-by: David Lechner > > --- > > drivers/iio/adc/ad7380.c | 52 ++++++++++++++++++++++++++++++++++++++++= +------ > > - > > 1 file changed, 45 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/iio/adc/ad7380.c b/drivers/iio/adc/ad7380.c > > index abd746aef868..5c5d2642a474 100644 > > --- a/drivers/iio/adc/ad7380.c > > +++ b/drivers/iio/adc/ad7380.c > > @@ -133,6 +133,7 @@ struct ad7380_state { > > struct spi_device *spi; > > struct regulator *vref; > > struct regmap *regmap; > > + struct spi_message *msg; > > /* > > * DMA (thus cache coherency maintenance) requires the > > * transfer buffers to live in their own cache lines. > > @@ -231,19 +232,55 @@ static int ad7380_debugfs_reg_access(struct iio_d= ev > > *indio_dev, u32 reg, > > return ret; > > } > > > > +static int ad7380_buffer_preenable(struct iio_dev *indio_dev) > > +{ > > + struct ad7380_state *st =3D iio_priv(indio_dev); > > + struct spi_transfer *xfer; > > + int ret; > > + > > + st->msg =3D spi_message_alloc(1, GFP_KERNEL); > > + if (!st->msg) > > + return -ENOMEM; > > + > > + xfer =3D list_first_entry(&st->msg->transfers, struct spi_transfe= r, > > + transfer_list); > > + > > + xfer->bits_per_word =3D st->chip_info->channels[0].scan_type.real= bits; > > + xfer->len =3D 4; > > + xfer->rx_buf =3D st->scan_data.raw; > > + > > + ret =3D spi_optimize_message(st->spi, st->msg); > > + if (ret) { > > + spi_message_free(st->msg); > > + return ret; > > + } > > + > > + return 0; > > +} > > + > > +static int ad7380_buffer_postdisable(struct iio_dev *indio_dev) > > +{ > > + struct ad7380_state *st =3D iio_priv(indio_dev); > > + > > + spi_unoptimize_message(st->msg); > > + spi_message_free(st->msg); > > + > > + return 0; > > +} > > + > > Not such a big deal but unless I'm missing something we could have the > spi_message (+ the transfer) statically allocated in struct ad7380_state = and do > the optimize only once at probe (naturally with proper devm action for > unoptimize). Then we would not need to this for every buffer enable + dis= able. I > know in terms of performance it won't matter but it would be less code I = guess. > > Am I missing something? No, your understanding is correct for the current state of everything in this series. So, we could do as you suggest, but I have a feeling that future additions to this driver might require that it gets changed back this way eventually.