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Date: Tue, 13 Feb 2024 18:57:19 +0200
From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>, 
	Andy Lutomirski <luto@kernel.org>, Peter Zijlstra <peterz@infradead.org>, 
	Isaku Yamahata <isaku.yamahata@intel.com>, x86@kernel.org, linux-kernel@vger.kernel.org, 
	Juergen Gross <jgross@suse.com>
Subject: Re: [PATCH, RESEND] x86/pat: Simplifying the PAT programming protocol
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On Tue, Feb 13, 2024 at 05:15:14PM +0100, Borislav Petkov wrote:
> On Thu, Feb 01, 2024 at 12:17:32AM +0200, Kirill A. Shutemov wrote:
> > > So the "relaxation" is the removal of that CR0.CD requirement?
> 
> So I'm looking at the SDM, revisions 081US and 082US.
> 
> Section
> 
> "12.11.8 MTRR Considerations in MP Systems"

The point is that PAT programming doesn't need to follow MTRR
considerations anymore.

Previously "Programming the PAT" section had this:

   The operating system is responsible for ensuring that changes to a PAT
   entry occur in a manner that maintains the consistency of the processor
   caches and translation lookaside buffers (TLB). This is accomplished by
   following the procedure as specified in Section 12.11.8, “MTRR
   Considerations in MP Systems,” for changing the value of an MTRR in a
   multiple processor system. It requires a specific sequence of
   operations that includes flushing the processors caches and TLBs.

The new version points to MTTR consideration as one of possible way to
invalidate TLB and caches:

  The operating system (OS) is responsible for ensuring that changes to a
  PAT entry occur in a manner that maintains the consistency of the
  processor caches and translation lookaside buffers (TLB). It requires the
  OS to invalidate all affected TLB entries (including global entries) and
  all entries in all paging-structure caches. It may also require flushing
  of the processor caches in certain situations. This can be accomplished
  in various ways, including the sequence below or by following the
  procedure specified in Section 12.11.8, “MTRR Considerations in MP
  Systems.” (See Section 4.10.4, “Invalidation of TLBs and
  Paging-Structure Caches” for additional background information.) Also
  note that in a multi-processor environment, it is the software's
  responsibility to resolve differences in conflicting memory types across
  logical processors that may arise from changes to the PAT (e.g., if two
  logical processors map a linear address to the same physical address but
  have PATs that specify a different memory type for that physical
  address).

The new text follows with example of sequence that flushes TLB and
caches. And it doesn't touch CR0.CD.

-- 
  Kiryl Shutsemau / Kirill A. Shutemov